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AD1941 Datasheet(PDF) 4 Page - Analog Devices

Part # AD1941
Description  SigmaDSP-TM Multichannel 28-Bit Audio Processor
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1941 Datasheet(HTML) 4 Page - Analog Devices

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AD1941
Preliminary Technical Data
Rev. PrE | Page 4 of 32
DIGITAL TIMING
Table 5 Digital Timing1
Parameter
Comments
Min
Max
Unit
tMP
MCLK Period
512 fS mode
36
244
ns
tMP
MCLK Period
384 fS mode
48
366
ns
tMP
MCLK Period
256 fS mode
73
488
ns
tMP
MCLK Period
64 fS mode
291
1953
ns
tMP
MCLK Period
Bypass mode
12
ns
tMDC
MCLK Duty Cycle
Bypass mode
40
60
%
tBIL
BCLK_IN LO Pulse Width
4
ns
tBIH
BCLK_IN HI Pulse Width
2
ns
tLIS
LRCLK_IN Setup
To BCLK_IN rising
12
ns
tLIH
LRCLK_IN Hold
From BCLK_IN rising
0
ns
tSIS
SDATA_INx Setup
To BCLK_IN rising
3
ns
tSIH
SDATA_INx Hold
From BCLK_IN rising
2
ns
tLOS
LRCLK_OUTx Setup
Slave mode
2
ns
tLOH
LRCLK_OUTx Hold
Slave mode
2
ns
tTS
BCLK_OUTx Falling to
LRCLK_OUTx Timing Skew
2
ns
tSODS
SDATA_OUTx Delay
Slave mode, from BCLK_OUTx falling
17
ns
tSODM
SDATA_OUTx Delay
Master mode, from BCLK_OUTx falling
17
ns
tRLPW
RESETB LO Pulse Width
10
ns
1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 32.
PLL
Table 6.
Parameter
Min
Typ
Max
Unit
Lock Time
3
20
ms
REGULATOR
Table 7.
Parameter
Min
Typ
Max
Unit
VSENSE Output Voltage
2.25
2.5
2.68
V



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