AD1941 datasheet(22/32 Pages) AD

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AD1941

Preliminary Technical Data

Rev. PrE | Page 22 of 32

used with ADI-supplied blocks. For normal operation, this

RAM to use the autoincrement feature. This feature is included

for maximum programming flexibility and may be used in the

case of specialized software development.

CONTROL PORT READ/WRITE DATA FORMATS

The read/write formats of the control port are designed to be

byte-oriented. This allows for easy programming of common

microcontroller chips. In order to fit into a byte-oriented

format, 0s are appended to the data fields before the MSB in

order to extend the data word to the next multiple of eight bits.

For example, 28-bit words written to the parameter RAM are

appended with four leading 0s in order to reach 32 bits

(4 bytes); 40-bit words written to the program RAM are not

appended with any 0s because it is already a full 5 bytes. These

zero-extended data fields are appended to a 3-byte field

consisting of a 7-bit chip address, a read/write bit, and an 11-bit

RAM/register address. The control port knows how many data

bytes to expect based on the address that is received in the first

three bytes.

The total number of bytes for a single-location write command

can vary from four bytes (for a control register write), to eight

bytes (for a program RAM write). Burst mode may be used to

fill contiguous register or RAM locations. A burst mode write is

done by writing the address and data of the first RAM/register

location to be written. Rather than ending the control port

transaction (by bringing the CLATCH signal high in the

AD1941, after the data word, as would be done in a single-

address write, the next data word can be written immediately

without first writing its specific address. The AD1941 control

port auto-increments the address of each write, even across the

boundaries of the different RAMs and registers.

Table 21. Parameter RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes 4–6

chip_adr [6:0], W/R

0000, param_adr[11:8]

param_adr[7:0]

0000, param[27:24]

param [23:0]

Table 22. Parameter RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Byte 3

Bytes 4–6

Byte 7

Byte 11

chip_adr [6:0], W/R

0000, param_adr[11:8]

param_adr[7:0]

0000, param[27:24]

param[23:0]

Byte 8

Byte 12

Byte 9

Byte 13

Byte 10

Byte 14

<—param_adr—>

param_adr + 1

param_adr + 2

Table 23. Program RAM Read/Write Format (Single Address)

Byte 0

Byte 1

Byte 2

Bytes 3–7

chip_adr [6:0], W/R

0000, prog_adr[11:8]

prog_adr[7:0]

prog[39:0]

Table 24. Program RAM Block Read/Write Format (Burst Mode)

Byte 0

Byte 1

Byte 2

Byte 3-7

Byte 8

Byte 13

chip_adr [6:0], W/R

0000, prog_adr[11:8]

prog_adr[7:0]

prog[39:0]

Byte 9

Byte 14

Byte 10

Byte 15

Byte 11

Byte 16

Byte 12

Byte 17

<—prog_adr—>

prog_adr +1

prog_adr +2

Table 25. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)

Byte 0

Byte1

Byte 2

Byte 3

Byte 4

chip_adr [6:0], W/R

0000, reg_adr[11:8]

reg_adr[7:0]

data[15:8]

data[7:0]

Table 26. Control Register Read/Write Format (RAM Configuration, Serial Input)

Byte 0

Byte1

Byte 2

Byte 3

chip_adr [6:0], W/R

0000, reg_adr[11:8]

reg_adr[7:0]

data[7:0]

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