AD1941 datasheet(19/32 Pages) AD

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Preliminary Technical Data

AD1941

Rev. PrE | Page 19 of 32

TIME (ms)

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1

010

520

Figure 14. Slew RAM—Constant dB Update Plot

TIME (ms)

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1

010

Figure 15. Slew RAM—RC-Type Update Plot

TIME (ms)

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1

010

Figure 16 Slew RAM—Constant Time Update Plot, Full Scale

TIME (ms)

0.8

0.6

0.4

0.2

–0.6

–0.4

–0.2

–0.8

–1

010

Figure 17 Slew RAM—Constant Time Update Plot, Half Scale

Constant Time Update Math

Constant time math is accomplished by adding a step value that

is calculated after each new target is loaded. The equation for

this step size is

Step

= (Target Data − Slew Data)/(Number of Steps)

Figure 16 shows a plot of the target/slew RAM operating in

constant time mode. For this example, 128 steps are used to

reach the target value. This type of ramping will take a fixed

amount of time for a given number of steps, regardless of the

difference in the initial state and the target value. Figure 17

shows a plot of a constant time ramp from –80 dB to –6 dB

(half scale) using 128 steps. You can see that the ramp takes the

same amount of time as the previous ramp from –80 dB to 0 dB.

SAFELOAD REGISTERS

Many applications require real-time control of signal processing

parameters, such as filter coefficients, mixer gains, multi-

channel virtualizing parameters, or dynamics processing curves.

To prevent instability from occurring, all of the parameters of a

biquad filter must be updated at the same time. Otherwise, the

filter could execute for one or two audio frames with a mix of

old and new coefficients. This mix could cause temporary

instability, leading to transients that could take a long time to

decay. To eliminate this problem, the AD1941 loads a set of

10 registers in the control port (five for 28-bit parameters, and

another five for indirectly addressing the target/slew RAMs)

with the desired parameter or target/slew RAM address and

data. Five registers are used because a biquad filter uses five

coefficients, and it is desirable to be able to do a complete

biquad update in one transaction. The safeload registers can be

used to update either the parameter RAM or target/slew RAM

values. Once these registers are loaded, the appropriate initiate

safe transfer bit (there are separate bits for parameter and

target/slew loads) in the core control register should be set to

initiate the loading into RAM. Program lengths should be

limited to 1,531 cycles (1,536 − 5) to ensure that the SigmaDSP

is able to perform the safeloads. It can be guaranteed that the

safeload will have occurred within one LRCLK period (21 µs at

fs = 48 kHz) of the initiate safe transfer bit being set.

The safeload logic automatically sends only those safeload regis-

ters that have been written to since the last safeload operation.

For example, if only two parameters are to be sent, only two of

the five safeload registers must be written to. When the initiate

safe transfer bit (in the core control register) is asserted, only

those two registers are sent; the other three registers are not sent

to the RAM and can still hold old or invalid data.

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