AD1941 datasheet(10/32 Pages) AD

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AD1941

Preliminary Technical Data

Rev. PrE | Page 10 of 32

FEATURES

The core of the AD1941 is a 28-bit DSP (56-bit with double

precision) optimized for audio processing.

The AD1941 contains a program RAM that is initialized from

an internal program ROM on power-up. The program RAM

can be loaded with a custom program after power-up. Signal

processing parameters are stored in a 1024-location parameter

RAM, which is initialized on power-up by an internal boot-

ROM. New values are written to the parameter RAM using the

control port. The values stored in the parameter RAM control

individual signal processing blocks, such as IIR equalization

filters, dynamics processors, audio delays, and mixer levels. A

safeload feature allows parameters to be transparently updated

without causing clicks on the output signals.

The target/slew RAM contains 64 locations and can be used as

channel volume controls or for other parameter updates. These

RAM locations take a target value for a given parameter and

ramp the current parameter value to the new value using a

specified time constant and one of a selection of linear or

logarithmic curves.

The AD1941 has a sophisticated control port that supports

complete read/write capability of all memory locations. Five

control registers (core, RAM configuration, Serial Output 0 to 7,

Serial Output 8 to 15, and serial input) are provided to offer

complete control of the chip’s configuration and serial modes.

Handshaking is included for ease of memory

uploads/downloads.

The AD1941 contains eight independent data capture circuits

that can be programmed to tap the signal flow of the processor

at any point in the DSP algorithm flow. Six of these captured

signals can be accessed by reading from the data capture

registers through the control port. The remaining two data

capture registers can be used to send any internal captured

signal to a stereo digital output signal on Pin SDATA_OUT7 for

driving external DACs or digital analyzers.

The AD1941 has very flexible serial data input/output ports that

allows for glueless interconnection to a variety of ADCs, DACs,

general-purpose DSPs, S/PDIF receivers, and sample rate

converters. The AD1941 can be configured in I2S, left-justified,

right-justified, or TDM serial port compatible modes. It can

support 16, 20, and 24 bits in all modes. The AD1941 accepts

serial audio data in MSB first and twos complement format.

The AD1941 operates from a single 2.5 V power supply. It is

fabricated on a single monolithic integrated circuit and is

housed in a 48-lead LQFP package for operation over the

–40°C to +105°C temperature range.

× 28

DSP CORE

DATA FORMAT:

5.23 (SINGLE PRECISION)

10.46 (DOUBLE PRECISION)

VOLTAGE REGULATOR

MEMORY CONTROLLERS

CONTROL

REGISITER

TRAP REG.

SAFELOAD

SERIAL

CONTROL

PORT

MCLK

PLL

DATA MEMORY

× 28

TARGET/SLEW

RAM

× 28

SERIAL

DATA/TDM

INPUT

GROUP

PLL MODE

SELECT

MASTER

CLOCK

INPUT

SPI I/O

GROUP

RESETB

PROGRAM

RAM

1536

× 40

PARAMETER

RAM

1024

× 28

COEFFICIENT

ROM

512

× 28

SERIAL DATA/

TDM OUTPUT

GROUP

REGULATOR

GROUP

Figure 6. Block Diagram

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