AD1941 datasheet(15/32 Pages) AD

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Preliminary Technical Data

AD1941

Rev. PrE | Page 15 of 32

condition. If an invalid subaddress is issued by the user, the

AD1941 does not issue an acknowledge and returns to the idle

condition. If the user exceeds the highest subaddress while in

autoincrement mode, one of two actions will be taken. In read

mode, the AD1941 outputs the highest subaddress register

contents until the master device issues a no-acknowledge,

indicating the end of a read. A no-acknowledge condition is

where the SDA line is not pulled low on the ninth clock pulse

on SCL. If the highest subaddress location is reached while in

write mode, the data for the invalid byte is not loaded into any

subaddress register, a no-acknowledge is issued by the AD1941,

and the part returns to the idle condition.

I2C Register/Memory Write Operation

Figure 9 shows the timing of a single-word write operation.

Every ninth clock, the AD1941 issues an acknowledge by

pulling its data line low.

Figure 10 shows the timing of a burst mode write sequence.

This figure shows an example where the target destination

registers are two bytes. The AD1941 knows to increment its sub-

address register every two bytes because the requested

subaddress corresponds to a register or memory area with a

2-byte word length.

The timing of a single word read operation is shown in

Figure 11. Note that the first R/W bit is still a 0, indicating a

write operation. This is because the subaddress still needs to be

written in order to set up the internal address. After the AD1941

acknowledges the receipt of the subaddress, the master must

issue a repeated start command followed by the chip address

byte with the R/W set to 1 (read). This causes the AD1941’s

SDA to turn around and begin driving data back to the master.

The master then responds every ninth pulse with an

acknowledge pulse to the AD1941.

Figure 12 shows the timing of a burst-mode read sequence. This

figure shows an example where the target read registers are two

bytes. The AD1941 knows to increment its subaddress register

every two bytes because the requested subaddress corresponds

to a register or memory area with word lengths of two bytes.

Other address ranges may have a variety of word lengths

ranging from one to five bytes; the AD1941 always decodes the

subaddress and sets the autoincrement circuit so that the

address increments after the appropriate number of bytes.

1–7

START ADDR

R/W

ACK

SUBADDR LOW

SUBADDR HI

ACK

DATA [7:0]

ACK

SDA

SCL

STOP

Figure 8. Single Byte I2C Write Timing

Chip Address,

R/W = 0

Subaddress

high

Subaddress

low

Data 0,

Byte 1

Data 0,

Byte 2

…

Data 0,

Byte N

Figure 9. Single-Word I2C Write

Chip

Address,

R/W = 0

Subaddress

high

Subaddress

low

Data

Byte 1

Data 0,

Byte 2

Data 1,

Byte 1

Data 1,

Byte 2

…

First Word

Second Word

Figure 10. Burst Mode I2C Write

Chip

Address,

R/W = 0

Subaddress

high

Subaddress

low

Chip

Addr,

R/W = 1

Data

0, Byte

Data

0, Byte

…

Data 0,

Byte N

Figure 11. Single Word I2C Read

Chip

Address,

R/W = 0

Subaddress

high

Subaddress

low

Chip

Address,

R/W = 1

Data 0,

Byte 1

Data 0,

Byte 2

…

First Word

Figure 12. Burst Mode I2C Read

S = Start Bit A(S) = Acknowledge by Slave

P = Stop Bit A(M) = Acknowledge by Master

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