AD1941 datasheet(26/32 Pages) AD

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AD1941

Preliminary Technical Data

Rev. PrE | Page 26 of 32

SERIAL OUTPUT CONTROL REGISTERS

Dither Enable (Bit 15)

Setting this bit to 1 enables dither on the appropriate channels.

Internally Link TDM Streams into Single 16-Channel Stream

(Bit 14, Serial Output Control Register 1)

When this bit is set to 1, the TDM output stream is output in a

single 16-channel stream on SDATA_OUT0. When set to 0,

TDM data is output on two independent 8-channel streams on

Pins SDATA_OUT0 and SDATA_OUT4.

Data Capture Serial Out Enable (Bit 14, Serial Output

Control Register 2)

When set to 1, SDATA_OUT7 is set as the output of the

data capture digital output registers (2640–2641). See the

Data Capture Registers section for a full explanation of using

this mode.

LRCLK Polarity (Bit 13)

When set to 0, the left channel data is clocked when LRCLK is

low, and the right data clocked when LRCLK is high. When set

to 1, this is reversed.

BCLK Polarity (Bit 12)

This bit controls on which edge of the bit clock the output data

is clocked. Data changes on the falling edge of BCLK_OUTx

when this bit is set to 0, and on the rising edge when this bit is

set at 1.

Master/Slave (Bit 11)

This bit sets whether the output port is a clock master or slave.

The default setting is slave; on power-up, Pins BCLK_OUTx

and LRCLK_OUTx are set as inputs until this bit is set to 1, at

which time they become clock outputs.

BCLK Frequency (Bits 10:9)

When the output port is being used as a clock master, these bits

set the frequency of the output bit clock, which is divided down

from the internal 73.728 MHz core clock.

Frame Sync Frequency (Bits 8:7)

When the output port is used as a clock master, these bits set the

frequency of the output word clock on the LRCLK_OUTx

pins, which is divided down from the internal 73.728 MHz

core clock.

Frame Sync Type (Bit 6)

This bit sets the type of signal on the LRCLK_OUTx pins.

When set to 0, the signal is a word clock with a 50% duty cycle;

when set to 1, the signal is a pulse with a duration of one bit

clock at the beginning of the data frame.

Serial Output/TDM Mode Control (Bit 5)

Setting this bit to 1 changes the output port from multiple serial

outputs to a single TDM output stream on the appropriate

SDATA_OUTx pin. This bit must be set in both serial output

control registers to enable 16-channel TDM on SDATA_OUT0.

MSB Position (Bits 4:2)

These three bits set the position of the MSB of data with respect

to the LRCLK edge. The data output of the AD1941 is always

MSB first.

Output Word Length (Bits 1:0)

These bits set the word length of the output data-word. All bits

following the LSB are set to 0.

Table 35. Serial Input Control Register (2646)

Function

8-/16-channel TDM input

0 = Dual 8-channel TDM

1 = 16-channel TDM input

LRCLK polarity

0 = Frame begins on falling edge

1 = Frame begins on rising edge

BCLK polarity

0 = Data changes on falling edge

1 = Data changes on rising edge

2:0

Serial Input Mode

000 = I2S

001 = Left-justified

010 = TDM

011 = Right-justified, 24-bit

100 = Right-justified, 20-bit

101 = Right-justified, 18-bit

110 = Right-justified, 16-bit

SERIAL INPUT CONTROL REGISTER

8-/16-Channel TDM Input (Bit 5)

Setting this bit to 0 puts the AD1941 into dual 8-channel

TDM input mode, with the two streams coming in on

SDATA_IN2/TDM_IN1 and SDATA_IN3/TDM_IN0.

Channels 0 to 7 will be input on TDM_IN0 and Channels 8

to 15 will come in on TDM_IN1. Setting this bit to 1 puts the

part in 16-channel TDM input mode, input on TDM_IN1.

LRCLK Polarity (Bit 4)

When set to 0, the left channel data on the SDATA_INx pins is

clocked when LRCLK_IN is low; and the right input data

clocked when LRCLK_IN is high. When set to 1, this is

reversed. In TDM mode, when this bit is set to 0, data is clocked

in starting with the next appropriate BCLK edge (set in Bit 3 of

this register) following a falling edge on the LRCLK_IN pin.

When set to 1 and running in TDM mode, the input data is

valid on the BCLK edge following a rising edge on the word

clock (LRCLK_IN). The serial input port can also operate with

a pulse input signal, rather than a clock. In this case, the first

edge of the pulse is used by the AD1941 to start the data frame.

When this polarity bit is set to 0, a low pulse should be used,

and a high pulse should be used when the bit it set to 1.

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