AD1941 datasheet(24/32 Pages) AD

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AD1941

Preliminary Technical Data

Rev. PrE | Page 24 of 32

SERIAL DATA INPUT/OUTPUT PORTS

The AD1941’s flexible serial data input and output ports can be

set to accept or transmit data in 2-channel formats or in an

8- or 16-channel TDM stream. Data is processed in twos

complement, MSB-first format. The left channel data field

always precedes the right channel data field in the 2-channel

streams. In the TDM modes, Slots 0 to 3 (8-channel TDM) or

Slots 0 to 7 (16-channel TDM) fall in the first half of the audio

frame, and Slots 4 to 7 (or Slots 8 to 15 in 16-channel TDM) are

in the second half of the frame. The serial modes are set in the

serial output and serial input control registers.

The input control register allows control of clock polarity and

data input modes. The valid data formats are I2S , left-justified,

right-justified (24-, 20-, 18-, or 16-bit), 8-channel, and

16-channel TDM. In all modes except for the right-justified

modes, the serial port will accept an arbitrary number of

bits up to a limit of 24. Extra bits will not cause an error, but

they will be truncated internally. Proper operation of the right-

justified modes requires that there be exactly 64 BCLKs per

audio frame. The TDM data is input on SDATA_IN2 and

SDATA_IN3 when in 2 × 8-channel TDM mode, and on

SDATA_IN2 in 16-channel TDM mode. The LRCLK in TDM

mode can be input to the AD1941 as either a 50/50 duty cycle

clock or as a bit-wide pulse.

The two clock domains on the serial output ports can generate

two separate 8-channel TDM streams or one 16-channel TDM

stream. When in 16-channel TDM mode, the data is clocked by

LRCLK_OUT0 and BCLK_OUT0. The AD1941 must be in

slave mode for 16-channel TDM unless the data is sampled at

48 kHz; the part cannot generate a TDM bit clock that is fast

enough to support 96 kHz or 192 kHz. In 8-channel TDM

mode, the AD1941 can be a master for 48 kHz and 96 kHz data,

but not for 192 kHz data. Table 31 displays the modes in which

the serial output port will function.

The output control registers give the user control of clock

polarities, clock frequencies, clock types, and data format. In all

modes except for the right-justified modes (MSB delayed by 8,

12, or 16), the serial port accepts an arbitrary number of bits up

to a limit of 24. Extra bits will not cause an error, but will be

truncated internally. Proper operation of the right-justified

modes requires the LSB to align with the edge of the LRCLK.

The default settings of all serial port control registers

correspond to 2-channel I2S mode. LRCLK_OUT0 and

BCLK_OUT0 are clocks for Serial Output Ports 0 to 7, and

LRCLK_OUT1 and BCLK_OUT1 Clock Ports 8 to 15.

All registers default to being set as all 0s. All register settings

apply to both master and slave modes unless otherwise noted.

Table 32 shows the proper configurations for standard audio

data formats.

Table 31 Serial Output Port Master/Slave Mode Capabilities

2-Channel Modes (I2S, Left-Justified, Right-Justified)

8-Channel TDM

16-Channel TDM

48 kHz

Master and slave

96 kHz

Master and slave

Slave only

192 kHz

Master and slave

Slave only

Table 32. Data Format Configurations

Format

LRCLK Polarity

LRCLK Type

BCLK Polarity

MSB Position

I2S (Figure 18)

Frame begins on

falling edge

Clock

Data changes on falling edge

Delayed from LRCLK edge by one BCLK

Left-Justified

(Figure 19)

Frame begins on

rising edge

Clock

Data changes on falling edge

Aligned with LRCLK edge

Right-Justified

(Figure 20)

Frame begins on

rising edge

Clock

Data changes on falling edge

Delayed from LRCLK edge by 8, 12, or 16 BCLKs

TDM with Clock

(Figure 21)

Frame begins on

falling edge

Clock

Data changes on falling edge

Delayed from start of word clock by one BCLK

TDM with Pulse

(Figure 22)

Frame begins on

rising edge

Pulse

Data changes on falling edge

Delayed from start of word clock by one BCLK

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