AD1941 datasheet(23/32 Pages) AD

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Preliminary Technical Data

AD1941

Rev. PrE | Page 23 of 32

Table 27. Data Capture Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

chip_adr [6:0], W/R

0000, data_capture_adr[11:8]

data_capture_adr[7:0]

000, progCount[10:6]1

progCount[5:0]1, regSel[1:0]2

1 ProgCount[10:0] = value of program counter where trap occurs (the table of values is generated by the program compiler).

2 RegSel[1:0] selects one of four registers (see Data Capture Registers section).

Table 28. Data Capture (Control Port Readback) Register Read Format

Byte 0

Byte 1

Byte 2

Bytes 3–5

chip_adr [6:0], W/R

0000, data_capture_adr[11:8]

data_capture_adr[7:0]

data[23:0]

Table 29. Safeload Register Data Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Bytes 4–7

chip_adr [6:0], W/R

0000, safeload_adr[11:8]

safeload_adr[7:0]

000000, data[33:32]

data[31:0]

Table 30. Safeload Register Address Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

chip_adr [6:0], W/R

0000, safeload_adr[11:8]

safeload_adr[7:0]

000000, param_adr[9:8]

param_adr[7:0]

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