AD1941 datasheet(17/32 Pages) AD

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Preliminary Technical Data

AD1941

Rev. PrE | Page 17 of 32

RECOMMENDED PROGRAM/PARAMETER

LOADING PROCEDURES

When writing large amounts of data to the program or para-

meter RAM in direct write mode, the processor core should be

disabled to prevent unpleasant noises from appearing at the

audio output. The AD1941 contains several mechanisms for

disabling the core.

If the loaded program does NOT use the target/slew RAM as

the main system volume control (for example, the default

power-up program)

Assert Bit 9 (LOW to assert—default setting) and Bit 6

(HIGH to assert) of the core control register. This zeroes

the accumulators, the serial output registers, and the serial

input registers.

Fill the program RAM using burst mode writes.

Fill the parameter RAM using burst mode writes.

Assert Bit 7 of the core control register to initiate a data-

memory clear sequence. Wait at least 100 µs for this

sequence to complete. This bit is automatically cleared after

the operation is complete.

Deassert Bit 9 and Bit 6 of the core control register to allow

the core to begin normal operation

If the loaded program does use the target/slew RAM as the

main system volume control:

Assert Bit 12 of the core control register. This begins a

volume ramp-down, with a time constant determined by

the upper bits of the target RAM. Wait for this ramp-down

to complete (the user may poll Bit 13 of the core control

Assert Bit 9 (LOW to assert) and Bit 6 (HIGH to assert) of

the core control register. This zeroes the accumulators, the

serial output registers, and the serial input registers.

Fill the program RAM using burst-mode writes.

Fill the parameter RAM using burst-mode writes.

Assert Bit 7 of the core control register to initiate a data-

memory clear sequence. Wait at least 100 µs for this

sequence to complete. This bit is automatically cleared after

the operation is complete.

Deassert Bit 9 and Bit 6 of the core control register.

If the newly loaded program also uses the target/slew

RAM, deassert Bit 12 of the core control register to begin a

volume ramp-up procedure.

TARGET/SLEW RAM

The target/slew RAM is a bank of 64 RAM locations, each of

which can each be set to autoramp from one value to a desired

final value in one of four modes.

Summary

The target/slew RAM is used by the DSP when a program is

loaded into the program RAM that uses one or more locations

in the slew RAM to access internal coefficient data. Typically,

these coefficients are used for volume controls or smooth cross-

fading effects, but may be used to update any value in the para-

meter RAM. Each of the 64 locations in the slew RAM are

linked to corresponding locations in the target RAM. When a

new value is written to the target RAM using the control

port, the corresponding slew RAM location begins to ramp

toward the target. The value is updated once per audio frame

(LRCLK period).

The target RAM is 34 bits wide. The lower 28 bits contain the

target data in 5.23 format for the linear and exponential

(constant dB and RC-type) ramp types. For constant time

ramping, the lower 28 bits contain 16 bits in 2.14 format and 12

bits to set the current step. The upper six bits are used to

determine the type and speed of the ramp envelope in all

modes. The format of the data write for linear and exponential

formats is shown in Table 14. Table 15 shows the data write

format for the constant time ramping.

Data can only be written to the target/slew RAM using the

safeload registers as described in the Safeload Registers section.

A mute slew RAM bit is included in the core control register to

simultaneously set all the slew RAM target values to 0. This is

useful for implementing a global multichannel mute. When this

bit is deasserted, all slew RAM values will return to their

original pre-muted states.

Table 14. Linear, Constant dB, and RC-type

Ramp Data Write

Byte 0

Byte 1

Bytes 2–4

000000,

curve_type[1:0]

time_const[3:0],

data[27:24]

data[23:0]

Table 15. Constant Time Ramp Data Write

Byte 0

Byte 1

Bytes 2–4

000000,

curve_type[1:0]

update_step[0],

#_of_steps[2:0], data[15:12]

data[11:0],

reserved[11:0]

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