AD1941 datasheet(20/32 Pages) AD

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AD1941

Preliminary Technical Data

Rev. PrE | Page 20 of 32

Table 17. Data Capture Control Registers (2634–2641)

Function

12:2

11-Bit Program Counter Address

1:0

00 = Mult_X_input

01 = Mult_Y_input

10 = MAC_output

11 = Accum_fback

DATA CAPTURE REGISTERS

The AD1941’s data capture feature allows the data at any node

in the signal processing flow to be sent to one of six control

port-readable registers or to a serial output pin. This can be

used to monitor and display information about internal signal

levels or compressor/limiter activity.

The AD1941 contains six independent control port-readable

data capture registers, and two digital output capture registers.

The digital output registers are output on SDATA_OUT7 when

the data capture serial out enable bit (Bit 14) is set in Serial

Output Control Register 2. These registers are useful when

debugging the signal processing flow.

For each of the data capture registers, a capture count and a

between 0 and 1,535 that corresponds to the program step

number where the capture will occur. The register select field

programs one of four registers in the DSP core that will be

transferred to the data capture register when the program

counter equals the capture count. The register select field

selections are shown in Table 18.

Table 18. Data Capture Output Register Select

Setting

Multiplier X Input (Mult_X_input)

Multiplier Y Input (Mult_Y_input)

Multiplier-Accumulator Output (MAC_out)

Accumulator Feedback (Accum_fback)

The capture count and register select bits are set by writing to

one of the eight data capture registers at register addresses

2634: Control Port Data Capture Setup Register 0

2635: Control Port Data Capture Setup Register 1

2636: Control Port Data Capture Setup Register 2

2637: Control Port Data Capture Setup Register 3

2638: Control Port Data Capture Setup Register 4

2639: Control Port Data Capture Setup Register 5

2640: Digital Out Data Capture Setup Register 0

2641: Digital Out Data Capture Setup Register 1

The captured data is in 5.19 twos complement data format for

all eight register select fields. The four LSBs are truncated from

the internal 5.23 data-word.

The data that must be written to set up the data capture is a

concatenation of the 11-bit program count index with the 2-bit

that correspond to the desired point to be monitored in the

signal processing flow can be found in a file output from the

program compiler. The capture registers can be accessed by

reading from locations 2634 to 2639 (for control port capture

registers). The format for reading and writing to the data

capture registers can be seen in Table 27 and Table 28.

Table 19. DSP Core Control Register (2642)

Function

15:14

Reserved

Slew RAM Muted (Read Only)

Mute Slew RAM, All Locations

Reserved, Set to 0

Use Serial Out LRCLK for Output Latch

Clear Internal Registers to All 0s, Active Low

Force Multiplier to 0

Inititalize Data Memory with 0s

Mute Serial Input Port

Initiate Safe Transfer to Target RAM

Initiate Safe Transfer to Parameter RAM

3:2

Input Serial Port to Sequencer Sync

00 = LRCLK

01 = LRCLK/2

10 = LRCLK/4

11 = LRCLK/8

1:0

Program Length

00 = 1536

01 = 768

10 = 384

11 = 192

DSP CORE CONTROL REGISTER

The controls in this register set the operation of the AD1941’s

DSP core. Bits 6 to 9 can be set to initiate a shutdown of the

core. The output is muted when this is performed, so it is best to

first assert the mute slew RAM bit (if slew RAM locations are

used as volume controls in the program) to avoid a click or pop

when shutdown is asserted.

Slew RAM Muted (Bit 13)

This bit is set to 1 when the slew RAM mute operation has been

completed. This bit is read-only and is automatically cleared by

reading.

Mute Slew RAM, All Locations (Bit 12)

Setting this bit to 1 initiates a mute of all 64 slew RAM

locations. When reset to 0, all RAM locations return to their

previous state. This bit is only functional if slew RAM locations

are used in the custom program design. Keep in mind that the

AD1941’s default program does not use any slew RAM volume

controls, so this bit has no effect in that case. The mute

operation is identical to writing all 0s to the data portion of the

target RAM, and therefore the time constant and linear/

exponential curve selection is determined by the bits that have

been previously written to the high bits of the target RAM.

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