AD1941 datasheet(14/32 Pages) AD

14 / 32 page

AD1941

Preliminary Technical Data

Rev. PrE | Page 14 of 32

CONTROL PORT

OVERVIEW

The AD1941 has many different control options that can be set

through an I2C interface. Most signal processing parameters are

controlled by writing new values to the parameter RAM using the

control port. Other functions, such as mute and input/ output

mode control, are programmed by writing to the control registers.

The control port is capable of full read/write operation for all of

the memories and registers. All addresses may be accessed in

both a single-address mode or a burst mode. A control word

consists of the chip address, the register/RAM subaddress, and

the data to be written. The data can be variable in its byte width.

The first byte of a control word (Byte 0) contains the 7-bit chip

address plus the R/W bit. The next two bytes (Bytes 1 and 2)

together form the subaddress of the memory or register

location within the AD1941. This subaddress needs to be two

bytes because the memories within the AD1941 are directly

addressable, and their sizes exceed the range of single-byte

addressing. All subsequent bytes (Bytes 3, 4, etc.) contain the

data, such as control port data or program or parameter data.

The AD1941 has several mechanisms for updating signal

processing parameters in real time without causing pops or

clicks. In cases where large blocks of data need to be down-

loaded, the output of the DSP core can be halted (using Bit 9 of

the core control register), new data loaded, and then restarted.

This is typically done during the booting sequence at start-up or

when loading a new program into RAM. In cases where only a

few parameters need to be changed, they can be loaded without

halting the program. To avoid unwanted side effects while

loading parameters on the fly, the SigmaDSP provides the

safeload registers. The safeload registers can be used to buffer a

full set of parameters (e.g. the five coefficients of a biquad) and

then transfer these parameters into the active program within

one audio frame. The safeload mode uses internal logic to

prevent contention between the DSP core and the control port.

I2C PORT

The AD1941 supports a 2-wire serial (I2C compatible) micro-

processor bus driving multiple peripherals. Two inputs, serial

data (SDA) and serial clock (SCL), carry information between

the AD1941 and the system I2C master controller. The AD1941

is always a slave on the I2C bus, which means that it will never

initiate a data transfer. Each slave device is recognized by a

unique address. The AD1941 has four possible slave addresses,

two for writing operations and two for reading. These are

unique addresses for the device and are illustrated in Table 11.

The LSB of the byte sets either a read or write operation; Logic

Level 1 corresponds to a read operation, and Logic Level 0

corresponds to a write operation. The seventh bit of the address

is set by tying the ADR_SEL pin of the AD1941 to Logic Level 0

or Logic Level 1.

The AD1941 I2C port uses a spike filter which can be enabled or

disabled by the I2C_FILT_ENB pin. Enabling this filter

guarantees that all isolated spikes, both positive and negative,

less than 50 ns wide will be removed from the I2C signal. The

filter is active when the I2C_FILT_ENB pin is low, and is

disabled when the pin is at a high logic level.

Table 11. I2C Address for AD1941

ADR_SEL

R/W

Slave Address

0x28

0x29

0x2A

0x2B

Initially, all devices on the I2C bus are in an idle state, which is

where the devices monitor the SDA and SCL lines for a start

condition and the proper address. The I2C master initiates a

data transfer by establishing a Start condition, defined by a

high-to-low transition on SDA while SCL remains high. This

indicates that an address/data stream will follow. All devices on

the bus respond to the start condition and shift the next eight

bits (7-bit address + R/W bit) MSB first. The device that

recognizes the transmitted address responds by pulling the data

line low during the ninth clock pulse. This ninth bit is known as

an acknowledge bit. All other devices withdraw from the bus at

this point and return to the idle condition. The R/W bit

determines the direction of the data. A logic 0 on the LSB of the

first byte means the master will write information to the

peripheral. A logic 1 on the LSB of the first byte means the

master will read information from the peripheral. A data

transfer takes place until a stop condition is encountered. A stop

condition occurs when SDA transitions from low to high while

SCL is held high. Figure 8 shows the timing of a single-byte I2C

write.

Burst mode addressing, where the subaddresses are automati-

cally incremented at word boundaries, can be used for writing

large amounts of data to contiguous memory locations. This

increment happens automatically if a stop condition is not

encountered after a single-word write. The registers and

memories in the AD1941 range in width from one to five bytes,

so the autoincrement feature knows the mapping between sub-

addresses and the word length of the destination register (or

memory location). A data transfer is always terminated by a

stop condition.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, these cause an

immediate jump to the idle condition. During a given SCL high

period, the user should only issue one start condition, one stop

condition, or a single stop condition followed by a single start

AD1941 Datasheet(PDF) 14 Page - Analog Devices

AD1941 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL