ADPD4200 datasheet(35/93 Pages) AD

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Data Sheet

ADPD4200

APPLICATIONS INFORMATION

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Rev. 0 | 35 of 93

Figure 32. Multiple Integration Mode with LED as Stimulus

Table 21. Relevant Settings for Multiple Integration Mode

Group

Time Slot A Register Address1

Bit Field Name

Description

Multiple Integration Mode

Using LED as Stimulus

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Leave at the default setting (0) for default sampling mode.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0DA for TIA, BPF, integrator, and ADC.

0x0102, Bits[15:12], 0x0103,

Bits[3:0]

INPxx_x

Enable desired inputs.

0x0103, Bits[14:12]

PRECON_x

Set to 0x5 to precondition anode of the photodiode to TIA_VREF.

0x0103, Bits[7:6], 0x0103, Bits[1:0] VCx_SEL_x

Set to 0x2 to set ~250 mV reverse bias across photodiode.

0x0104, Bits[5:0]

TIA_GAIN_CHx_x

Select TIA gain.

0x0104, Bits[9:8]

AFE_TRIM_VREF_x

Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range.

Timing

0x0107, Bits[15:8]

NUM_INT_x

Set to a number that utilizes most of the dynamic range of integrator

available, leaving some margin for fluctuations in input level.

0x0107, Bits[7:0]

NUM_REPEAT_x

Set NUM_REPEAT_x to the number of times to repeat the multiple

integration sequence. SNR increases by a factor of √(NUM_REPEAT_x).

Total number of pulses is equal to NUM_REPEAT_x × NUM_INT_x.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to LED_WIDTH_x + 1.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time = INTEG_OFFSET_x. Optimize as described

in the Optimizing Position of Integration Sequence section.

LED Settings

0x0105, Bit 15, 0x0105, Bit 7,

0x0106, Bit 15, and 0x0106, Bit 7

LED_DRIVESIDEx_x

Select LED for time slot used.

0x0105, Bits[14:8], 0x0105,

Bits[6:0], 0x0106, Bits[14:8],

0x0106, Bits[6:0]

LED_CURRENTx_x

Set LED current for selected LED.

0x0109, Bits[7:0]

LED_OFFSET_x

Sets start time of first LED pulse in 1 μs increments and 0x10 default (16

μs).

0x0109, Bits[15:8]

LED_WIDTH_x

Sets width of LED pulse in 1 μs increments, and 2 μs or 3 μs recommended.

1 This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location

for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at

Address 0x0160, and so on.

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