ADPD4200 datasheet(27/93 Pages) AD

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Data Sheet

ADPD4200

APPLICATIONS INFORMATION

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Rev. 0 | 27 of 93

Table 16. Single Integration Mode Settings

Group

Time Slot A Register Address1

Bit Field Name

Description

0x0105, Bits[14:8], 0x0105, Bits[6:0],

0x0106, Bits[14:8], 0x0106, Bits[6:0]

LED_CURRENTx_x

Set LED current for selected LED.

1 This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for

SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address

0x0160, and so on.

Optimizing Position of Integration Sequence

It is critical that the zero crossing of the output response of the

BPF be aligned with the integration sequence such that the positive

integration is aligned with the positive portion of the BPF output

response and the negative integration is aligned with the negative

portion of the BPF output response (see Figure 25).

A simple test to find the zero crossing is to setup the circuit so

that the LED is reflecting off a reflector at a fixed distance from

the photodiode such that a steady dc level of photodiode current

is provided to the ADPD4200. Monitor the output while sweeping

the integrator offset, INTEG_OFFSET_x[12:5], from a low value to

a high value in 1 μs steps. The zero crossing is located when a

relative maxima is seen at the output. The zero crossing can then

be identified with much finer precision by sweeping the INTEG_

OFFSET_x[4:0] bit field in 31.25 ns increments.

The optimal timing point is a function of TIA bandwidth that varies

with TIA gain. To achieve the maximum SNR at each TIA gain

setting, it is recommended that the user find the optimal timing point

at each TIA gain setting for a given use case. Because there is

minimal part to part variation in this optimal timing point, that same

integrator offset timing for each gain setting can be used for all

parts. If the user must use the same integrator timing for all TIA

gain settings without re-optimizing for each TIA gain setting, the

200 kΩ TIA gain optimal timing must be used for the other TIA gain

settings.

Improving SNR Using Multiple Pulses

The ADPD4200 use short LED pulses, on the order of 2 μs or

3 μs. The SNR of a single pulse is approximately 68 dB to

74 dB, depending on the TIA gain. The SNR can be extended

to ~100 dB by increasing the number of pulses per sample and

filtering to a relevant signal bandwidth, for example, 0.5 Hz to 20 Hz

for a heart rate signal. The SNR increases as the square root of the

number of pulses. Thus, for every doubling of pulses, 3 dB of SNR

increase is achieved. The number of pulses is increased with the

NUM_REPEAT_x bit field.

Improving SNR Using Integrator Chopping

The last stage in the ADPD4200 datapath is a charge integrator.

The integrator uses an on and off integration sequence, synchron-

ized to the emitted light pulse, which acts as an additional high-

pass filter to remove offsets, drifts, and low frequency noise

from the previous stages. However, the integrating amplifier can

itself introduce low frequency signal content at a low level. The

ADPD4200 has a mode that enables additional chopping in the

digital domain to remove this signal. Chopping is achieved by using

an even number of pulses per sample and inverting the integration

sequence for half of those sequences. When the math is done to

combine the digitized result of each of the pulses of the sample,

the sequences with an inverted integrator sequence are subtracted,

and the sequences with a normal integrator sequence are added.

An example diagram of the integrator chopping sequence is shown

in Figure 26.

The result of chopping is that any low frequency signal contribution

from the integrator is eliminated, leaving only the integrated signal

and resulting in higher SNR, especially at higher numbers of pulses

and at lower TIA gains where the noise contribution of the integrator

becomes more pronounced.

Digital chopping is enabled using the registers and bits detailed in

Table 17. The bit fields define the chopping operation for the first

four pulses. This 4-bit sequence is then repeated for all subsequent

sequence of four pulses. In Figure 26, a sequence is shown where

the second and fourth pulses are inverted while the first and third

pulses remain in the default polarity (noninverted). This configura-

tion is achieved by setting the REVERSE_INTEG_x bit field =

0xA to reverse the integration sequence for the second and fourth

pulses. To complete the operation, the math must be adjusted by

setting the SUBTRACT_x bit field = 0xA. An even number of pulses

must be used with integrator chop mode.

When using integrator chop mode, the ADC offset bit fields,

CH1_ADC_ADJUST_x and CH2_ADC_ADJUST_x, must be set

to 0 because, when the math is adjusted to subtract the inverted

integration sequences while the default integration sequences are

added, any digital offsets at the output of the ADC are automatical-

ly eliminated. Integrator chop mode also eliminates the need to

manually null the ADC offsets at startup in a typical application.

Note that the elimination of the offset using chop mode can clip at

least half of the noise signal when no input signal is present, which

makes it difficult to measure the noise floor during characterization

of the system. Three options for performing noise floor characteri-

zation of the system include the following:

►

Chop mode disabled.

►

Chop mode enabled but with a minimal signal present at the

input, which increases the noise floor enough such that it is no

longer clipped.

ADPD4200 Datasheet(PDF) 27 Page - Analog Devices

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