ADPD4200 datasheet(16/93 Pages) AD

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Data Sheet

ADPD4200

THEORY OF OPERATION

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Figure 18. Example of the Average LED Forward-Biased Voltage Drop as a

Function of the LED Driver Current Setting

To correctly size the CVLED capacitor, do not deplete it during the

pulse of the LED to the point where the voltage on the capacitor

is less than the forward bias on the LED. Calculate the minimum

value for CVLED as follows:

CVLED= tLED_PW×ILED_MAX/

VLED_MIN− VFB_LED_MAX+VCOMP

(1)

where:

tLED_PW is the LED pulse width.

ILED_MAX is the maximum forward-biased current on the LED used

in operating the devices.

VLED_MIN is the lowest voltage from the VLEDx supply with no load.

VFB_LED_MAX is the maximum forward-biased voltage required on

the LED to achieve ILED_MAX.

VCOMP is the compliance voltage of the LED driver at the program-

med LED drive level.

The numerator of Equation 1 sets up the total discharge amount in

coulombs from the bypass capacitor to satisfy a single programmed

LED pulse of the maximum current. The denominator represents

the difference between the lowest voltage from the VLEDx supply

and the LED required voltage. The LED required voltage is the

voltage of the anode of the LED such that the compliance of the

LED driver and the forward-biased voltage of the LED operating at

the maximum current is satisfied. At a 125 mA drive current, the

compliance voltage of the driver is ~0.4 V. For a typical ADPD4200

example, assume that the lowest value for the VLEDx supply is

4.5 V, and that the peak current is 125 mA for two 528 nm LEDs in

parallel. The minimum value for CVLED is then equal to 1 µF.

CVLED= 3×10−6×0.125/

4.5− 3.5+0.4 =0.625 μF

(2)

As shown in Equation 2, as the minimum supply voltage drops

close to the maximum anode voltage, the demands on CVLED

become more stringent, forcing the capacitor value higher. It is

important to insert the correct values into Equation 2. For example,

using an average value for VLED_MIN instead of the worst case value

for VLED_MIN can cause a serious design deficiency, resulting in a

CVLED value that is too small, causing insufficient optical power in

the application.

Additionally, multiple pulses can cause further droop on the VLEDx

supply if the CVLED capacitor is not fully recharged between pulses.

Therefore, adding a sufficient margin on CVLED is strongly recom-

mended. Add additional margin to CVLED to account for multiple

pulses and derating of the capacitor value over voltage, bias,

temperature, and other factors over the life of the component.

DATAPATH, DECIMATION, SUBSAMPLING,

AND FIFO

ADC samples are gathered for each pulse in each time slot and

combine to create a running positive and negative sum for each

time slot. These sums are each kept as a 32-bit unsigned value

sample is added to either the positive or negative sum based on the

SUBTRACT_x bits for the current pulse in standard sampling mode,

or in the lit or dark acquisition regions for digital integration mode. In

impulse mode, the positive sum is used to add two values and the

result is written directly to the FIFO. Figure 19 shows the datapath

structure.

At the end of the pulse operations in each time slot, the signal value

is calculated by subtracting the negative accumulator from the

positive accumulator. The signal and dark values are then clipped

to positive numbers and are processed by the decimation unit. If

the decimated value is ready, the data registers update, and the

selected values are written to the FIFO. The data interrupt for that

time slot is also set at this time.

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