CS47L85 datasheet(159/370 Pages) CIRRUS

159 / 370 page

CS47L85

Rev 4.3

159

DSP GPIO

The CS47L85 supports up to 40 GPIO pins, which can be assigned to application-specific functions. There are 8 dedicated

GPIO pins, and a further 32 GPIOs that are implemented as alternate functions to a pin-specific capability.

The GPIOs can be used to provide status outputs and control signals to external hardware; the supported functions include

Interrupt (IRQ) output, FLL Clock output, Accessory Detection status, and S/PDIF or PWM-coded audio channels. See

“General Purpose Input / Output” for further details.

The GPIOs can support miscellaneous logic input and output, interfacing directly with the integrated DSPs, or with the Host

Application software. A basic level of I/O func

tionality is described in the “General Purpose Input / Output” section, under

the configuration where GPn_FN = 001h. (The GPn_FN register selects the functionality for the respective pin, GPIOn.)

The DSP GPIO function provides an advanced I/O capability, supporting the requirements of the CS47L85 as a multi-

purpose sensor hub. The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected

combinations of GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in

hardware. In a typical use case, one GPIO mask is defined for each DSP, or for each functional process; this provides a

highly efficient mechanism for each DSP to independently access the respective input and output signals.

The DSP GPIO function is selected by setting GPn_FN = 002h

for the respective GPIO pin (where ‘n’ identifies the applicable

GPIOn pin).

Each DSP GPIO is controlled using register bits that determine the direction (input/output) and the logic state (0/1) of the

pin. These register bits are replicated in 8 control ‘sets’; each of the control sets has the capability to determine the logic

level of any DSP GPIO.

Mask bits are provided within each control set, to determine which of the control sets has control of each DSP GPIO. To

avoid logic contention, a DSP GPIO output must be controlled (unmasked) in a maximum of one control set at any time.

Note that write access to the direction control bits (DSPGPn_SETx_DIR) and level control bits (DSPGPn_SETx_LVL) is only

valid when the channel (DSPGPn) is unmasked in the respective control set. Register writes to these fields will be

implemented for the unmasked DSP GPIOs, and will be ignored in respect of the masked DSP GPIOs. Note that the level

control bits (DSPGPn_SETx_LVL) are provide output level control only; they cannot be used for input readback.

The logic level of the unmasked DSP GPIO outputs in any control set are typically configured using a single register write.

(GPIOs 1 to 32 are set in a single operation; a separate register write is required for GPIOs 33 to 40.) Writing to these

registers will determine the logic level of the unmasked DSP GPIOs in that set only; all other outputs are unaffected.

Status bits are provided, for readback of DSP GPIO inputs. There is only one set of status bits, indicating the logic level of

every input or output pin that is configured as a DSP GPIO. (Note that, for any pin configured as a GPIO input, with GPn_FN

= 001h, the applicable DSPGPn_STS bit will also provide valid readback of the pin status.)

The status bits will also indicate the logic level of the DSP GPIO outputs. The respective pins are driven as outputs if

configured as a DSP GPIO output, and unmasked in one of the control sets. Note that a DSP GPIO will continue to be driven

as an output, even if the mask bit is subsequently asserted in that set. The pin will only cease to be driven if it is configured

as a DSP GPIO input, and is unmasked in one of the control sets, or else if the pin is configured as an input, under a different

GPn_FN register selection.

The DSP GPIO functions are implemented alongside the ‘standard’ GPIO capability, providing an alternative method of

maskable I/O control for all of the GPIO pins. The DSP GPIO control bits in the register map are implemented in a manner

that supports efficient read/write access for multiple GPIOs at once.

The DSP GPIO logic is illustrated in Figure 45, also showing

the control registers that are common to the ‘standard’ GPIO.

The DSP GPIO function is selected by setting GPn_FN = 002h for the respective GPIO pin. Integrated pull-up and pull-down

resistors are provided on each of the GPIO pins, which are also valid fo

r DSP GPIO function. A ‘bus keeper’ function is

supported on the GPIO pins; this is enabled using the respective pull-up and pull-down control bits. The bus keeper function

holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tri-stated). See Table 94 for details of the

GPIO pull-up and pull-down control bits.

CS47L85 Datasheet(PDF) 159 Page - Cirrus Logic

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