CS47L85 datasheet(156/370 Pages) CIRRUS

156 / 370 page

CS47L85

156

Rev 4.3

TIMERn_REFCLK_SRC

DSPCLK

32k Clock

MCLK1

MCLK2

SYSCLK

ASYNCCLK

GPIO1

GPIO2

GPIO3

GPIO4

f = TIMERn count rate

If DSPCLK is enabled, and a clock

source other than DSPCLK is selected,

≤ DSPCLK/3, f ≤ 12MHz

Divider

TIMERn_PRESCALE

Divide by 1, 2, 4, 8

… 128

Divider

TIMERn_REFCLK_DIV

Divide by 1, 2, 4, 8

… 64

except DSPCLK

Divider

TIMERn_REFCLK_FREQ_SEL

DSPCLK / SYSCLK /

ASYNCCLK only

Figure 44 General Purpose Timer

The Timer control registers are described in Table 35.

BIT

LABEL

DEFAULT

DESCRIPTION

Timer 1 Base Address = R311296 (4C000h)

Timer 2 Base Address = R311424 (4C080h)

Timer 3 Base Address = R311552 (4C100h)

Timer 4 Base Address = R311680 (4C180h)

Timer 5 Base Address = R311808 (4C200h)

Timer 6 Base Address = R311936 (4C280h)

Timer 7 Base Address = R312064 (4C300h)

Timer 8 Base Address = R312192 (4C380h)

base address

Timern_Control

TIMERn_CONTINUOUS

Timer Continuous Mode select

0 = Single mode

1 = Continuous mode

Timer must be stopped

(TIMERn_RUNNING_STS=0) when

updating this register

TIMERn_DIR

Timer Count Direction

0 = Down

1 = Up

Timer must be stopped

(TIMERn_RUNNING_STS=0) when

updating this register

18:16

TIMERn_PRESCALE [2:0]

000

Timer Count Rate Prescale

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

Timer must be stopped

(TIMERn_RUNNING_STS=0) when

updating this register

CS47L85 Datasheet(PDF) 156 Page - Cirrus Logic

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