CS47L85 datasheet(155/370 Pages) CIRRUS

155 / 370 page

CS47L85

Rev 4.3

155

GENERAL PURPOSE TIMERS

The CS47L85 incorporates 8 general purpose timers, which support a wide variety of possible uses. In particular, these

timers provide essential support for the sensor hub capability. The timers allow time stamp information to be associated with

external sensor activity, and other system events, enabling real time data to be more easily integrated into user applications.

The timers allow many advanced functions to be implemented with a high degree of autonomy from a host processor.

The timers can use either internal system clocks, or external clock signals, as a reference. The selected reference is scaled

down, using configurable dividers, to the required clock count frequency.

The reference clock for each Timer is selected using TIMERn_REFCLK_SRC, (where ‘n’ identifies the applicable Timer, 1

through to 8).

If SYSCLK, ASYNCCLK, or DSPCLK is selected, then a lower clock frequency, derived from the applicable system clock,

can be selected using the TIMERn_REFCLK_FREQ_SEL register. The applicable division ratio is determined automatically,

assuming the respective clock source has been correctly configured as described in the “Clocking and Sample Rates”

section.

If any source other than DSPCLK is selected, then the clock can be further divided using the TIMERn_REFCLK_DIV register.

Division ratios in the range 1 to 128 can be selected.

Note that, if DSPCLK is enabled, then the CS47L85 will synchronise the selected reference clock to DSPCLK. As a result

of this, if a non-DSPCLK is selected as source, the following additional constraints must be observed: the reference clock

frequency (after TIMERn_REFCLK_FREQ_SEL and after TIMERn_REFCLK_DIV) must be less than DSPCLK / 3, and must

be less than 12MHz; it must also be close to 50% duty cycle. The TIMERn_REFCLK_DIV register can be used to ensure

that these criteria are met.

One final division, controlled by TIMERn_PRESCALE, determines the Timer count frequency. This register is valid for all

clock reference sources; division ratios in the range 1 to 128 can be selected. The output from this division corresponds to

the frequency at which the TIMERn_COUNT registers are incremented (or decremented).

The maximum count value of the Timer is determined by the TIMERn_MAX_COUNT field. This is the final count value (when

counting up), or the initial count value (when counting down). The current value of the Timer counter can be read from the

TIMERn_CUR_COUNT field.

The Timer is started by writing ‘1’ to the TIMERn_START bit. Note that, if the Timer is already running, it will re-start from

its initial value. The Timer is stopped by writing ‘1’ to the TIMERn_STOP bit. The count direction (up or down) is selected

using the TIMERn_DIR bit.

The TIMERn_CONTINUOUS bit selects whether the Timer automatically re-

starts after the ‘end of count’ condition has been

reached. The TIMERn_RUNNING_STS indicates whether the Timer is running, or if it has stopped.

Note that the Timers should be stopped before making any changes to the respective configuration registers. The Timer

configuration should only be changed when TIMERn_RUNNING_STS=0.

The reference clock for each Timer should be configured and enabled before starting the Timer, and whenever the Timer is

running. If the reference clock is interrupted while the Timer is running, the Timer operation pauses, and resumes again

when the clock restarts.

See “Clocking and Sample Rates” for details of the system clocks (including requirements for

reconfiguring SYSCLK or DSPCLK while DSP peripherals are enabled).

The Timer status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event after the final count

value is reached -

see “Interrupts”. Note that the Interrupt does not occur immediately when the final count value is reached;

the Interrupt is triggered at the point when the next update to the Timer count value would be due.

The Timer status can be output directly on a GPIO pin as an external indication of the Timer activity. See “General Purpose

Input / Output

” to configure a GPIO pin for this function.

The Timers can be used as a

Watchdog function to trigger a shutdown of the Class D speaker drivers. See “Thermal

Shutdown and Short Circuit Protection

” to configure this function.

The Timer block is illustrated in Figure 44.

CS47L85 Datasheet(PDF) 155 Page - Cirrus Logic

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