CS47L85 datasheet(157/370 Pages) CIRRUS

157 / 370 page

CS47L85

Rev 4.3

157

BIT

LABEL

DEFAULT

DESCRIPTION

14:12

TIMERn_REFCLK_DIV [2:0]

000

Timer Reference Clock Divide

(Not valid for DSPCLK source).

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

If DSPCLK is enabled, and DSPCLK

is not selected as source, then the

output frequency from this divider

must be set less than or equal to

DSPCLK/3, and less than or equal to

12MHz.

If DSPCLK is disabled, then the output

of this divider will be used as clock

reference for any associated Event

Logger. In this case, the divider output

corresponds to the frequency of Event

Logging opportunities on the

respective module(s).

Timer must be stopped

(TIMERn_RUNNING_STS=0) when

updating this register

10:8

TIMERn_REFCLK_FREQ_S

EL [2:0]

000

Timer Reference Frequency Select

Only valid when SYSCLK,

ASYNCCLK, or DSPCLK is the

source. The selected frequency must

be less than or equal to the frequency

of the respective source.

SYSCLK or ASYNCCLK source:

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

All other codes are Reserved

DSPCLK source:

000 = 5.5MHz to 9.375MHz

001 = 9.375MHz to 18.75MHz

010 = 18.75MHz to 37.5MHz

011 = 37.5MHz to 75MHz

All other codes are Reserved

Note that, because DSPCLK could be

any frequency (within the valid

ranges), it is not possible to quote

exact frequencies in this register

definition. The exact frequency will be

derived as DSPCLK divided by 1, 2, 4,

8, or 16.

Timer must be stopped

(TIMERn_RUNNING_STS=0) when

updating this register.

CS47L85 Datasheet(PDF) 157 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 157 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL