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CS47L85 Datasheet(PDF) 153 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 153 Page - Cirrus Logic |
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153 / 370 page  CS47L85 Rev 4.3 153 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION READ 8:0 EVENTLOGn_FIFO13_ID [8:0] 000h Event Log FIFO Index 13 source Register description is as above. base address +B6h EVENTLOGn_FIFO13_ TIME 31:0 EVENTLOGn_FIFO13_TIM E [31:0] 0000 0000h Event Log FIFO Index 13 Time base address +B8h EVENTLOGn_FIFO14_ READ 12 EVENTLOGn_FIFO14_POL 0 Event Log FIFO Index 14 polarity Register description is as above. 8:0 EVENTLOGn_FIFO14_ID [8:0] 000h Event Log FIFO Index 14 source Register description is as above. base address +BAh EVENTLOGn_FIFO14_ TIME 31:0 EVENTLOGn_FIFO14_TIM E [31:0] 0000 0000h Event Log FIFO Index 14 Time base address +BCh EVENTLOGn_FIFO15_ READ 12 EVENTLOGn_FIFO15_POL 0 Event Log FIFO Index 15 polarity Register description is as above. 8:0 EVENTLOGn_FIFO15_ID [8:0] 000h Event Log FIFO Index 15 source Register description is as above. base address +BEh EVENTLOGn_FIFO15_ TIME 31:0 EVENTLOGn_FIFO15_TIM E [31:0] 0000 0000h Event Log FIFO Index 15 Time Table 33 Event Logger (EVENTLOGn) Control A list of the valid input sources for the Event Loggers is provided in Table 34. The “EDGE” type noted is coded as “S” (single edge) or “D” (dual edge). Note that a single-edge input source will only provide valid input to the Event Logger in the default (Rising Edge Triggered) polarity. It is advised to take care when enabling IRQ1 or IRQ2 as an input source for the Event Loggers; a recursive loop, where the IRQ signal is also an output from the same Event Logger, must be avoided. ID DESCRIPTION EDGE ID DESCRIPTION EDGE ID DESCRIPTION EDGE 3 irq1 D 259 gpio4 D 354 event3_full S 4 irq2 D 260 gpio5 D 355 event4_full S 9 sysclk_fail S 261 gpio6 D 356 event5_full S 24 fll1_lock D 262 gpio7 D 357 event6_full S 25 fll2_lock D 263 gpio8 D 358 event7_full S 26 fll3_lock D 264 gpio9 D 359 event8_full S 32 frame_start_g1r1 S 265 gpio10 D 368 event1_wmark S 33 frame_start_g1r2 S 266 gpio11 D 369 event2_wmark S 34 frame_start_g1r3 S 267 gpio12 D 370 event3_wmark S 40 frame_start_g2r1_sys S 268 gpio13 D 371 event4_wmark S 41 frame_start_g2r2_sys S 269 gpio14 D 372 event5_wmark S 80 hpdet S 270 gpio15 D 373 event6_wmark S 88 micdet S 271 gpio16 D 374 event7_wmark S 96 jd1_rise S 272 gpio17 D 375 event8_wmark S 97 jd1_fall S 273 gpio18 D 384 dsp1_dma S 98 jd2_rise S 274 gpio19 D 385 dsp2_dma S 99 jd2_fall S 275 gpio20 D 386 dsp3_dma S 100 micd_clamp_rise S 276 gpio21 D 387 dsp4_dma S 101 micd_clamp_fall S 277 gpio22 D 388 dsp5_dma S 128 drc1_sig_det D 278 gpio23 D 389 dsp6_dma S 129 drc2_sig_det D 279 gpio24 D 390 dsp7_dma S |
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