CS47L85 datasheet(308/370 Pages) CIRRUS

308 / 370 page

CS47L85

308

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

FLL1_SYNC_DF

SAT

FLL1 Synchroniser Bandwidth

0 = Wide bandwidth

1 = Narrow bandwidth

Table 109 FLL1 Register Map

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R401

(0191h)

FLL2_Con

trol_1

FLL2_ENA

FLL2 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL2 enable

sequence, i.e., after the other FLL registers have been

configured.

R402

(0192h)

FLL2_Con

trol_2

FLL2_CTRL_UP

FLL2 Control Update

Write ‘1’ to apply the FLL2_N and FLL2_THETA register

settings.

(Only valid when FLL2_ENA=1)

9:0

FLL2_N [9:0]

008h

FLL2 Integer multiply for FREF

(LSB = 1)

If updated while the FLL is enabled, the new value is

only effective when a ‘1’ is written to FLL2_CTRL_UPD.

R403

(0193h)

FLL2_Con

trol_3

15:0

FLL2_THETA

[15:0]

0018h

FLL2 Fractional multiply for FREF

This field sets the numerator (multiply) part of the

FLL2_THETA / FLL2_LAMBDA ratio.

Coded as LSB = 1.

If updated while the FLL is enabled, the new value is

only effective when a ‘1’ is written to FLL2_CTRL_UPD.

R404

(0194h)

FLL2_Con

trol_4

15:0

FLL2_LAMBDA

[15:0]

007Dh

FLL2 Fractional multiply for FREF

This field sets the denominator (dividing) part of the

FLL2_THETA / FLL2_LAMBDA ratio.

Coded as LSB = 1.

R405

(0195h)

FLL2_Con

trol_5

11:8

FLL2_FRATIO

[3:0]

FLL2 FVCO clock divider

0h = 1

1h = 2

2h = 3

3h = 4

…

Fh = 16

R406

(0196h)

FLL2_Con

trol_6

7:6

FLL2_REFCLK_

DIV [1:0]

FLL2 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be divided down

to <=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

CS47L85 Datasheet(PDF) 308 Page - Cirrus Logic

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