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CS47L85 Datasheet(PDF) 307 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 307 Page - Cirrus Logic

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CS47L85
Rev 4.3
307
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R386
(0182h)
FLL1_Syn
chroniser_
2
9:0
FLL1_SYNC_N
[9:0]
000h
FLL1 Integer multiply for FSYNC
(LSB = 1)
R387
(0183h)
FLL1_Syn
chroniser_
3
15:0
FLL1_SYNC_TH
ETA [15:0]
0000h
FLL1 Fractional multiply for FSYNC
This field sets the numerator (multiply) part of the
FLL1_SYNC_THETA / FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R388
(0184h)
FLL1_Syn
chroniser_
4
15:0
FLL1_SYNC_LA
MBDA [15:0]
0000h
FLL1 Fractional multiply for FSYNC
This field sets the denominator (dividing) part of the
FLL1_SYNC_THETA / FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R389
(0185h)
FLL1_Syn
chroniser_
5
10:8
FLL1_SYNC_FR
ATIO [2:0]
000
FLL1 Synchroniser FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
R390
(0186h)
FLL1_Syn
chroniser_
6
7:6
FLL1_SYNCCLK
_DIV [1:0]
00
FLL1 Synchroniser Clock Reference Divider
00 = 1
01 = 2
10 = 4
11 = 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
3:0
FLL1_SYNCCLK
_SRC
0000
FLL1 Synchroniser Clock source
0000 = MCLK1
0001 = MCLK2
0011 = SLIMCLK
0100 = FLL1
0101 = FLL2
0110 = FLL3
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1011 = AIF4BCLK
1100 = AIF1LRCLK
1101 = AIF2LRCLK
1110 = AIF3LRCLK
1111 = AIF4LRCLK
All other codes are Reserved
R391
(0187h)
FLL1_Syn
chroniser_
7
5:2
FLL1_SYNC_GAI
N [3:0]
0000
FLL1 Synchroniser Gain
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 to 1111 = 256



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