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CS47L85 Datasheet(PDF) 310 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 310 Page - Cirrus Logic

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CS47L85
310
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R422
(01A6h)
FLL2_Syn
chroniser_
6
7:6
FLL2_SYNCCLK
_DIV [1:0]
00
FLL2 Synchroniser Clock Reference Divider
00 = 1
01 = 2
10 = 4
11 = 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
3:0
FLL2_SYNCCLK
_SRC
0000
FLL2 Synchroniser Clock source
0000 = MCLK1
0001 = MCLK2
0011 = SLIMCLK
0100 = FLL1
0101 = FLL2
0110 = FLL3
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1011 = AIF4BCLK
1100 = AIF1LRCLK
1101 = AIF2LRCLK
1110 = AIF3LRCLK
1111 = AIF4LRCLK
All other codes are Reserved
R423
(01A7h)
FLL2_Syn
chroniser_
7
5:2
FLL2_SYNC_GAI
N [3:0]
0000
FLL2 Synchroniser Gain
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 to 1111 = 256
0
FLL2_SYNC_DF
SAT
1
FLL2 Synchroniser Bandwidth
0 = Wide bandwidth
1 = Narrow bandwidth
Table 110 FLL2 Register Map
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R433
(01B1h)
FLL3_Con
trol_1
0
FLL3_ENA
0
FLL3 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the FLL3 enable
sequence, i.e., after the other FLL registers have been
configured.
R434
(01B2h)
FLL3_Con
trol_2
15
FLL3_CTRL_UP
D
0
FLL3 Control Update
Write ‘1’ to apply the FLL3_N and FLL3_THETA register
settings.
(Only valid when FLL3_ENA=1)
9:0
FLL3_N [9:0]
008h
FLL3 Integer multiply for FREF
(LSB = 1)
If updated while the FLL is enabled, the new value is
only effective when a ‘1’ is written to FLL3_CTRL_UPD.



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