CS47L85 datasheet(313/370 Pages) CIRRUS

313 / 370 page

CS47L85

Rev 4.3

313

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

FLL3_SYNC_DF

SAT

FLL3 Synchroniser Bandwidth

0 = Wide bandwidth

1 = Narrow bandwidth

Table 111 FLL3 Register Map

FREE-RUNNING FLL MODE

The FLL can generate a clock signal even when no external reference is available. This may be because the normal input

reference has been interrupted, or may be during a standby or start-up period when no initial reference clock is available.

Free-running FLL mode is enabled using the FLLn_FREERUN register. (Note that FLLn_ENA must also be enabled in Free-

running FLL mode.)

In Free-running FLL mode, the normal feedback mechanism of the FLL is halted, and the FLL oscillates independently of

the external input reference(s).

If the FLL was previously operating normally, (with an input reference clock), then the FLL output frequency will remain

unchanged when Free-running FLL mode is enabled. The FLL output will be independent of the input reference while

operating in free-running mode with FLLn_FREERUN=1.

The main FLL loop will always continue to free-run if the input reference clock is stopped (regardless of the FLLn_FREERUN

setting). If FLLn_FREERUN=0, the FLL will re-lock to the input reference whenever it is available.

In free-running mode, (with FLLn_FREERUN=1), the FLL integrator value (part of the feedback mechanism) can be

commanded directly using the FLLn_FRC_INTEG_VAL register. The integrator value in this register is applied to the FLL

when a ‘1’ is written to the FLLn_FRC_INTEG_UPD bit.

If the FLL is started up in free-running mode, (i.e., it was not previously running), then the default value of

FLLn_FRC_INTEG_VAL will be applied.

The FLL integrator value (part of the feedback mechanism) can be read from the FLLn_INTEG register; the value of this

field may be stored for later use. Note that the readback value of the FLLn_INTEG register is only valid when

FLLn_FREERUN=1, and the FLLn_INTEG_VALID bit is set.

The FLL integrator setting does not ensure a specific output frequency for the FLL across all devices and operating

conditions; some level of variation will apply.

The free-running FLL clock may be selected as the SYSCLK source or ASYNCCLK source as shown Figure 74.

The control registers applicable to Free-running FLL mode are described in Table 112.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R369

(0171h)

FLL1_Con

trol_1

FLL1_FREERUN

FLL1 Free-Running Mode Enable

0 = Disabled

1 = Enabled

The FLL feedback mechanism is halted in Free-Running

mode, and the latest integrator setting is maintained

R375

(0177h)

FLL1_Loo

p_Filter_T

est_1

FLL1_FRC_INTE

G_UPD

Write ‘1’ to apply the FLL1_FRC_INTEG_VAL setting.

(Only valid when FLL1_FREERUN=1)

11:0

FLL1_FRC_INTE

G_VAL [11:0]

281h

FLL1 Forced Integrator Value

R376

(0178h)

FLL1_NC

O_Test_0

FLL1_INTEG_VA

LID

FLL1 Integrator Valid

Indicates if the FLL1_INTEG register is valid

0 = Not valid

1 = Valid

11:0

FLL1_INTEG

[11:0]

000h

FLL1 Integrator Value (Read-only)

Indicates the current FLL1 integrator setting. Only valid

when FLL1_INTEG_VALID = 1.

R401

(0191h)

FLL2_Con

trol_1

FLL2_FREERUN

FLL2 Free-Running Mode Enable

0 = Disabled

1 = Enabled

The FLL feedback mechanism is halted in Free-Running

mode, and the latest integrator setting is maintained

CS47L85 Datasheet(PDF) 313 Page - Cirrus Logic

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