CS47L85 datasheet(316/370 Pages) CIRRUS

316 / 370 page

CS47L85

316

Rev 4.3

FLL INTERRUPTS AND GPIO OUTPUT

For each FLL, the CS47L85

supports an ‘FLL Lock’ signal which indicates whether FLL Lock has been achieved (i.e., the

FLL is locked to the input reference signal).

The FLL Lock signals are inputs to the Interrupt control circuit and can be used to trigger an Interrupt event -

see “Interrupts”.

Note that these Interrupt signals are de-bounced, and require clocking to be present in order to assert the respective Interrupt;

either the 32kHz clock, or the SYSCLK signal, must be enabled to trigger an Interrupt from the FLL signals.

The FLL Lock signals can be output directly on a GPIO pin as an external indication of th

e FLL status. See “General Purpose

Input / Output

” to configure a GPIO pin for these functions. (These GPIO outputs are not de-bounced, and do not require

clocking to be present.)

Clock output signals derived from the FLL can be output on a GPIO pin.

See “General Purpose Input / Output” to configure

a GPIO pin for this function.

The FLL clocking configuration is illustrated in Figure 76.

EXAMPLE FLL CALCULATION

The following example illustrates how to derive the FLL1 registers to generate an oscillator frequency (FVCO) of 294.912 MHz

from a 12.000 MHz reference clock (FREF). This is suitable for generating SYSCLK at 98.304 MHz, and/or DSPCLK at

147.456 MHz.

Note that, for the purposes of this calculation, it is assumed that the synchroniser is disabled.



Set FLL1_REFCLK_DIV in order to generate FREF <=13.5MHz:

FLL1_REFCLK_DIV = 00 (divide by 1)



Set FLL1_FRATIO for the given reference frequency as shown in Table 106:

FREF = 12MHz, therefore FLL1_FRATIO = 0h (divide by 1)



Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO x 3 x FREF):

N.K = 294.912 / (1 x 3 x 12) = 8.192



Confirm that a non-integer value has been calculated for N.K.



Confirm that the input frequency, FREF, is less than the applicable limit shown in Table 107.



Determine FLL1_N from the integer portion of N.K:-

FLL1_N = 8 (008h)



Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO x FREF, FVCO / 3):

GCD(FLL) = GCD(1 x 12000000, 294912000 / 3) = 96000



Determine FLL1_THETA, as given by

FLL1_THETA = ((FVCO / 3) - (FLL1_N x FLL1_FRATIO x FREF)) / GCD(FLL):

FLL1_THETA = ((294912000 / 3) - (8 x 1 x 12000000)) / 96000

FLL1_THETA = 24 (0018h)



Determine FLL_LAMBDA, as given by

FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL):

FLL1_LAMBDA = (1 x 12000000) / 96000

FLL1_LAMBDA = 125 (007Dh)

CS47L85 Datasheet(PDF) 316 Page - Cirrus Logic

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