CS47L85 datasheet(320/370 Pages) CIRRUS

320 / 370 page

CS47L85

320

Rev 4.3

4-WIRE (SPI) CONTROL MODE

The 4-wire (SPI) Control Interface mode is supported on CIF1 and CIF3, and uses the corresponding SS

¯¯ , SCLK, MOSI and

MISO pins.

In Write operations (R/W=0), the MOSI pin input is driven by the controlling device.

In Read operations (R/W=1), the MOSI pin is ignored following receipt of the valid register address.

When SS

¯¯ is asserted (logic 0), the MISO output is actively driven when outputting data, and is high impedance at other

times. When SS

¯¯ is not asserted, the MISO output is high impedance.

The high impedance state of the MISO output allows the pin to be shared with other slaves. An internal pull-down resistor

can be enabled on the CIF1MISO pin, as described in Table 117.

Data transfers on CIF1 or CIF3 must use the applicable SPI message format, according to the register address space that

is being accessed:



When accessing register addresses below R12288 (3000h), the applicable SPI protocol comprises a 31-bit



When accessing register addresses from R12888 (3000h) upwards, the applicable SPI protocol comprises a 31-

bit register address, and 32-bit data words.



Note that, in all cases, the complete SPI message protocol also includes a Read/Write bit, and a 16-

bit ‘padding’

phase (see Figure 77 and Figure 78 below).

Continuous read and write modes enable multiple register operations to be scheduled faster than is possible with single

register operations. In these modes, the CS47L85 will automatically increment the register address at the end of each data

word, for as long as SS

¯¯ is held low and SCLK is toggled. Successive data words can be input/output every 16 (or 32) clock

cycles (depending on the applicable register address space).

The 4-wire (SPI) protocol is illustrated in Figure 77 and Figure 78. Note that 16-bit data words are shown, but the equivalent

protocol also applies to 32-bit data words.

A30

MOSI

SCLK

31-bit register address

16-bit data word

R/W

A29

B14

B15

16-bit padding

Figure 77 Control Interface 4-wire (SPI) Register Write (16-bit Data Words)

A30

MOSI

SCLK

31-bit register address

16-bit data word

MISO

R/W

A29

B14

B15

16-bit padding

Figure 78 Control Interface 4-wire (SPI) Register Read (16-bit Data Words)

CS47L85 Datasheet(PDF) 320 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 320 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL