CS47L85 datasheet(319/370 Pages) CIRRUS

319 / 370 page

CS47L85

Rev 4.3

319

CONTROL INTERFACE

The CS47L85 is controlled by writing to its control registers. Readback is available for all registers. Three independent

Control Interfaces are provided, giving flexible capability as described below. Note that the SLIMbus interface also supports

read/write access to the CS47L85 control registers -

see “SLIMbus Interface Control”.

Interface function can be supported with or without system clocking - there is no requirement for SYSCLK, or any other

system clock, to be enabled when accessing the register map.

The CS47L85 executes a Boot Sequence following Power-On Reset (POR), Hardware Reset, Software Reset or Wake-Up

(from Sleep mode). Note that Control Register writes should not be attempted until the Boot Sequence has completed. See

“Power-On Reset (POR)” for further details.

A summary of the CS47L85 Control Interfaces is described in Table 116.

CONTROL

INTERFACE

DESCRIPTION

PIN FUNCTIONS

POWER

DOMAIN

CIF1

4-wire (SPI) interface

CIF1MISO - data output

CIF1MOSI - data input

CIF1SCLK - interface clock input

CIF1SS

¯¯¯¯¯¯ -

‘slave select’ input

DBVDD1

CIF2

2-wire (I2C) interface

CIF2SCLK - interface clock input

CIF2SDA - data input/output

DBVDD1

CIF3

4-wire (SPI) interface

CIF3MISO - data output

CIF3MOSI - data input

CIF3SCLK - interface clock input

CIF3SS

¯¯¯¯¯¯ -

‘slave select’ input

DBVDD3

Table 116 Control Interface Summary

The CS47L85 provides an integrated pull-down resistor on the CIF1MISO pin. This provides a flexible capability for

interfacing with other devices. The pull-down is enabled using the CIF1MISO_PD control bit, as described in Table 117.

Note that there is no pull-down available on the CIF3MISO pin. An external resistor (e.g., 47k

) should be used here, if

required.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

(0008h)

Ctrl_IF_C

FG_1

CIF1MISO_PD

CIF1MISO Pull-Down Control

0 = Disabled

1 = Enabled

Table 117 Control Interface Pull-Down

A detailed description of the 2-wire (I2C) interface and 4-wire (SPI) interface modes is provided in the following sections.

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