CS47L85 datasheet(321/370 Pages) CIRRUS

321 / 370 page

CS47L85

Rev 4.3

321

2-WIRE (I2C) CONTROL MODE

The 2-wire (I2C) Control Interface mode is supported on CIF2 only, and uses the corresponding SCLK, SDA pins.

In 2-wire (I2C) mode, the CS47L85 is a slave device on the control interface; SCLK is a clock input, while SDA is a bi-

directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the CS47L85

transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA

line high so that the logic 1 can be recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device ID

(this is not the same as the address of each register in the CS47L85).

The CS47L85 device ID is 0011_0100 (34h). Note that the LSB of the device ID is the Read/Write bit; this bit is set to logic

1 for “Read” and logic 0 for “Write”.

The CS47L85 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition

on SDA while SCLK remains high. This indicates that a device ID, and subsequent address/data byte(s), will follow. The

CS47L85 responds to the start condition and shifts in the next eight bits on SDA (8-bit device ID, including Read/Write bit,

MSB first). If the device ID received matches the device ID of the CS47L85, then the CS47L85 responds by pulling SDA low

on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the CS47L85 returns to the

idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the CS47L85, the data transfer continues as described below. The controller

indicates the end of data transfer with a low to high transition on SDA while SCLK remains high. After receiving a complete

address and data sequence the CS47L85 returns to the idle state and waits for another start condition. If a start or stop

condition is detected out of sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device

returns to the idle condition.

Data transfers on CIF2 must use the applicable I2C message format, according to the register address space that is being

accessed:



When accessing register addresses below R12288 (3000h), the applicable I2C protocol comprises a 32-bit



When accessing register addresses from R12888 (3000h) upwards, the applicable I2C protocol comprises a 32-

bit register address, and 32-bit data words.



Note that, in all cases, the complete I2C message protocol also includes a Device ID, a Read/Write bit, and other

signalling bits (see Figure 79 and Figure 80 below).

The CS47L85 supports the following read and write operations:



Single write



Single read



Multiple write



Multiple read

Continuous (multiple) read and write modes allow register operations to be scheduled faster than is possible with single

Successive data words can be input/output every 2 (or 4) data bytes, depending on the applicable register address space.

CS47L85 Datasheet(PDF) 321 Page - Cirrus Logic

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