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CS47L85 Datasheet(PDF) 322 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 322 Page - Cirrus Logic |
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322 / 370 page  CS47L85 322 Rev 4.3 The 2-wire (I2C) protocol for a single, 16-bit register write operation is illustrated in Figure 79. A25 D7 D1 A31 SDA SCLK device ID register address A15 – A8 A24 A15 A8 Note: The SDA pin is used as input for the control register address and data; SDA is pulled low by the receiving device to provide the acknowledge (ACK) response R/W A9 A7 register address A31 – A24 register address A7 – A0 START (Write) ACK ACK ACK A17 A23 A16 register address A23 – A16 ACK data bits B15 – B8 B15 B8 B1 B0 B9 B7 data bits B7 – B0 ACK ACK A1 A0 ACK STOP Figure 79 Control Interface 2-wire (I2C) Register Write (16-bit Data Words) The 2-wire (I2C) protocol for a single, 16-bit register read operation is illustrated in Figure 80. A25 D7 D1 A31 SDA SCLK device ID A24 Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses R/W register address A31 – A24 START (Write) ACK A17 A23 A16 register address A23 – A16 device ID D7 B9 B8 D1 B15 data bits B15 – B8 ACK ACK R/W (Read) B1 B0 B7 data bits B7 – B0 ACK STOP ACK Rpt START A1 A0 register address A7 – A0 register address A15 – A8 A15 A8 A9 A7 ACK ACK Figure 80 Control Interface 2-wire (I2C) Register Read (16-bit Data Words) The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 118. Note that 16-bit data words are shown in these illustrations. The equivalent protocol is also applicable to 32-bit words, with 4 data bytes transmitted (or received) instead of 2. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDA Low) A ¯¯ Not Acknowledge (SDA High) P Stop Condition R/W ¯¯ ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to CS47L85 [Grey field] Data flow from CS47L85 to bus master Table 118 Control Interface (I2C) Terminology Device ID S A Address Byte [3] (0) A 8 bit Device ID 8 bits Address Byte [2] A 8 bits RW Address Byte [1] A 8 bits A 8 bits MSByte Data A LSByte Data A P 8 bits 8 bits Address Byte [0] (Most Significant Byte) (Least Significant Byte) Figure 81 Single Register Write to Specified Address |
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