CS47L85 datasheet(324/370 Pages) CIRRUS

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CS47L85

324

Rev 4.3

CONTROL WRITE SEQUENCER

The Control Write Sequencer is a programmable unit that forms part of the CS47L85 control interface logic. It provides the

ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence

may be initiated by a single operation from the host processor and then left to execute independently.

Default sequences for pop-suppressed start-up and shut-down of each headphone/earpiece output driver are provided

(these are scheduled automatically when the respective output paths are enabled or disabled). Other control sequences can

be programmed, and may be associated with Sample Rate Detection, DRC, MICDET Clamp, or Event Logger status - these

sequences are automatically scheduled whenever a corresponding event is detected.

When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The

‘start index’ of a control

sequence

within the sequencer’s memory may be commanded directly by the host processor. The applicable ‘start index’

for each of the sequences associated with Sample Rate Detection, DRC, or MICDET Clamp, or Event Logger status is held

in a user-programmed control register.

The Control Write Sequencer may be triggered in a number of ways, as described above. Multiple sequences will be queued

if necessary, and each is scheduled in turn.

The Control Write Sequencer can be supported with or without system clocking - there is no requirement for SYSCLK, or

any other system clock, to be enabled when using the Control Write Sequencer. The timing accuracy of the sequencer

operation will be improved when SYSCLK is present, but the general functionality is supported with or without SYSCLK.

INITIATING A SEQUENCE

The Register fields associated with running the Control Write Sequencer are described in Table 119.

The CS47L85 provides 16 general purpose trigger bits for the Write Sequencer, to allow easy triggering of the associated

control sequences. Writing a ‘1’ to the trigger bit will initiate a control sequence, starting at the respective index position

within the Control Sequencer memory.

The WSEQ_TRG1_INDEX register defines the sequencer start index corresponding to the WSEQ_TRG1 trigger control bit.

Equivalent start index registers are provided for each of the trigger control bits, as described in Table 119. Note that a

sequencer start index of 1FFh will cause the respective sequence to be aborted.

The General Purpose control sequences are undefined following Power-On Reset (POR), Hardware Reset, or following a

Sleep mode transition. The General Purpose control sequences must be reconfigured by the host processor following any

of these events. Note that all control sequences are maintained in the sequencer memory through Software Reset.

The Write Sequencer can also be commanded using control bits in register R22 (16h). In this case, the Write Sequencer is

enabled using the WSEQ_ENA bit, and the index location of the first command in the sequence is held in the

WSEQ_START_INDEX register

. Writing a ‘1’ to the WSEQ_START bit commands the sequencer to execute a control

sequence, starting at the specified index position. Note that, if the sequencer is already running, then the WSEQ_START

command will be queued, and executed later when the sequencer becomes available.

Note that the mechanism for queuing multiple sequence requests has some limitations, when using the WSEQ_START bit

to trigger the write sequencer. If a sequence is initiated using the WSEQ_START bit, no other control sequences should be

triggered until the sequence completes. The WSEQ_BUSY bit (described in Table 125) provides an indication of the

sequencer status, and can be used to confirm that sequence has completed. Control sequences triggered by another other

method are queued if necessary, and scheduled in turn.

The Write Sequencer can be interrupted by writing a

‘1’ to the WSEQ_ABORT bit. Note that this command will only abort a

sequence that is currently running; if other sequence commands are pending and not yet started, these sequences will not

be aborted by writing to the WSEQ_ABORT bit.

The Write Sequencer stores up to 508 register write commands. These are defined in Registers R12288 (3000h) to R13302

(33F6h). See Table 126 for a description of these registers.

CS47L85 Datasheet(PDF) 324 Page - Cirrus Logic

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