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CS47L85 Datasheet(PDF) 317 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 317 Page - Cirrus Logic

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CS47L85
Rev 4.3
317
EXAMPLE FLL SETTINGS
Table 114 provides example FLL settings for generating an oscillator frequency (FVCO) of 294.912 MHz from a variety of low
and high frequency reference inputs. This is suitable for generating SYSCLK at 98.304 MHz, and/or DSPCLK at 147.456
MHz.
Note that, in these examples, it is assumed that the synchroniser is disabled.
FLL (Main Loop) Settings
FSOURCE
FVCO (MHz)
FREF
Divider
FRATIO
N.K
FLLn_N
FLLn_
THETA
FLLn_
LAMBDA
32.000 kHz
294.912
1
15
204.8
0CCh
0004h
0005h
32.768 kHz
294.912
1
16
187.5
0BBh
0001h
0002h
48 kHz
294.912
1
15
136.5333
088h
0008h
000Fh
128 kHz
294.912
1
7
109.4173
06Dh
0005h
0007h
512 kHz
294.912
1
5
38.4
026h
0002h
0005h
1.536 MHz
294.912
1
3
21.3333
015h
0001h
0003h
3.072 MHz
294.912
1
3
10.6667
00Ah
0002h
0003h
11.2896 MHz
294.912
1
1
8.7075
008h
0068h
0093h
12.000 MHz
294.912
1
1
8.192
008h
0018h
007Dh
12.288 MHz
294.912
2
3
5.3333
005h
0001h
0003h
13.000 MHz
294.912
1
1
7.5618
007h
0391h
0659h
19.200 MHz
294.912
2
1
10.24
00Ah
0006h
0019h
24 MHz
294.912
2
1
8.192
008h
0018h
007Dh
26 MHz
294.912
2
1
7.5618
007h
0391h
0659h
27 MHz
294.912
2
1
7.2818
007h
013Dh
0465h
FVCO = (FSOURCE / FREF Divider) * 3 * N.K * FRATIO
The N.K values are represented in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above.
See Table 109, Table 110 and Table 111 for the coding of the FLLn_REFCLK_DIV and FLLn_FRATIO registers.
Table 114 Example FLL Settings
– Synchroniser Disabled
Table 115 provides example FLL settings for generating SYSCLK at 98.304 MHz, and/or DSPCLK at 147.456 MHz, with the
synchroniser enabled. The main loop and the synchroniser loop must each be configured according to the respective input
source.



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