CS47L85 datasheet(311/370 Pages) CIRRUS

311 / 370 page

CS47L85

Rev 4.3

311

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R435

(01B3h)

FLL3_Con

trol_3

15:0

FLL3_THETA

[15:0]

0018h

FLL3 Fractional multiply for FREF

This field sets the numerator (multiply) part of the

FLL3_THETA / FLL3_LAMBDA ratio.

Coded as LSB = 1.

If updated while the FLL is enabled, the new value is

only effective when a ‘1’ is written to FLL3_CTRL_UPD.

R436

(01B4h)

FLL3_Con

trol_4

15:0

FLL3_LAMBDA

[15:0]

007Dh

FLL3 Fractional multiply for FREF

This field sets the denominator (dividing) part of the

FLL3_THETA / FLL3_LAMBDA ratio.

Coded as LSB = 1.

R437

(01B5h)

FLL3_Con

trol_5

11:8

FLL3_FRATIO

[3:0]

FLL3 FVCO clock divider

0h = 1

1h = 2

2h = 3

3h = 4

…

Fh = 16

R438

(01B6h)

FLL3_Con

trol_6

7:6

FLL3_REFCLK_

DIV [1:0]

FLL3 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be divided down to

<=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

3:0

FLL3_REFCLK_S

0000

FLL3 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

0110 = FLL3

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1011 = AIF4BCLK

1100 = AIF1LRCLK

1101 = AIF2LRCLK

1110 = AIF3LRCLK

1111 = AIF4LRCLK

All other codes are Reserved

R441

(01B9h)

FLL3_Con

trol_7

5:2

FLL3_GAIN [3:0]

0000

FLL3 Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000 to 1111 = 256

R449

(01C1h)

FLL3_Syn

chroniser_

FLL3_SYNC_EN

FLL3 Synchroniser Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL3

synchroniser enable sequence, i.e., after the other

synchroniser registers have been configured.

CS47L85 Datasheet(PDF) 311 Page - Cirrus Logic

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