CS47L85 datasheet(305/370 Pages) CIRRUS

305 / 370 page

CS47L85

Rev 4.3

305

Note that, in the above equations:

FSYNC is the synchroniser input frequency, after division by FLLn_SYNCCLK_DIV, where applicable

FLLn_SYNC_FRATIO is the FVCO clock ratio (1, 2, 4, 8 or 16)

The value of N (Sync) is held in the FLLn_SYNC_N register field.

The value of K (Sync) is determined by the FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA fields.

The FLLn_SYNC_N, FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA fields are all coded as integers (LSB = 1).

In Fractional Mode, with the synchroniser disabled (K > 0, and FLLn_SYNC_ENA = 0), the register fields FLLn_THETA and

FLLn_LAMBDA can be calculated as described below.

The equivalent procedure is also used to derive the FLLn_SYNC_THETA and FLLn_SYNC_LAMBDA register values from

the corresponding synchroniser parameters. (This is only required if the synchroniser is enabled.)

Calculate GCD(FLL) using the ‘Greatest Common Denominator’ function:

GCD(FLL) = GCD(FLLn_FRATIO x FREF, FVCO / 3)

where GCD(x, y) is the greatest common denominator of x and y

FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable.

Next, calculate FLLn_THETA and FLLn_LAMBDA using the following equations:

FLLn_THETA = ((FVCO / 3) - (FLL_N x FLLn_FRATIO x FREF)) / GCD(FLL)

FLLn_LAMBDA = (FLLn_FRATIO x FREF) / GCD(FLL)

Note that, in the operating conditions described above, the values of FLLn_THETA and FLLn_LAMBDA must be co-prime

(i.e., not divisible by any common integer). The calculation above ensures that the values will be co-prime. The value of K

must be a fraction less than 1 (i.e., FLLn_THETA must be less than FLLn_LAMBDA).

In Fractional Mode, with the synchroniser enabled (K > 0, and FLLn_SYNC_ENA = 1), the value of FLLn_THETA is

calculated as described below. The value of FLLn_LAMBDA is ignored in this case.

FLLn_THETA = K x 65536

The FLL control registers are described in Table 109, Table 110 and Table 111. Example settings for a variety of reference

frequencies and output frequencies are shown in Table 114.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R369

(0171h)

FLL1_Con

trol_1

FLL1_ENA

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL1 enable

sequence, i.e., after the other FLL registers have been

configured.

R370

(0172h)

FLL1_Con

trol_2

FLL1_CTRL_UP

FLL1 Control Update

Write ‘1’ to apply the FLL1_N and FLL1_THETA register

settings.

(Only valid when FLL1_ENA=1)

9:0

FLL1_N [9:0]

008h

FLL1 Integer multiply for FREF

(LSB = 1)

If updated while the FLL is enabled, the new value is

only effective

when a ‘1’ is written to FLL1_CTRL_UPD.

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