CS47L85 datasheet(301/370 Pages) CIRRUS

301 / 370 page

CS47L85

Rev 4.3

301

FREQUENCY LOCKED LOOP (FLL)

Three integrated FLLs are provided to support the clocking requirements of the CS47L85. These can be enabled and

configured independently according to the available reference clocks and the application requirements. The reference clock

may be a high frequency (e.g., 12.288MHz) or low frequency (e.g., 32.768kHz).

The FLL is tolerant of jitter and may be used to generate a stable output clock from a less stable input reference. The FLL

characteristics are summarised in “Electrical Characteristics”. Note that the FLL can be used to generate a free-running

clock in the absence of an external reference source. This is described in the “Free-Running FLL Mode” section below.

Configurable spread-spectrum modulation can be applied to the FLL outputs, to control EMI effects.

Each of the FLLs comprises two sub-systems -

the ‘main’ loop and the ‘synchroniser’ loop; these can be used together to

maintain best frequency accuracy and noise (jitter) performance across multiple use-cases. The two-loop design enables

the FLL to synchronise effectively to an input clock that may be intermittent or noisy, whilst also achieving the performance

benefits of a stable clock reference that may be asynchronous to the audio data.

The main loop takes a constant and stable clock reference as its input. For best performance, a high frequency (e.g.,

12.288MHz) reference is recommended. The main FLL loop will free-run without any clock reference if the input signal is

removed; it can also be configured to initiate an output in the absence of any reference signal.

The synchroniser loop takes a separate clock reference as its input. The synchroniser input may be intermittent (e.g., during

voice calls only). The FLL uses the synchroniser input, when available, as the frequency reference. To achieve the designed

performance advantage, the synchroniser input must be synchronous with the audio data.

Note that, if only a single clock input reference is used, this must be configured as the main FLL input reference. The

synchroniser should be disabled in this case.

The synchroniser loop should only be used when the main loop clock reference is present. If the input reference to the main

FLL is intermittent, or may be interrupted unexpectedly, then the synchroniser should be disabled.

The FLL is enabled using the FLLn_ENA register bit (where n = 1, 2 or 3 for the corresponding FLL). The FLL Synchroniser

is enabled using the FLLn_SYNC_ENA register bit.

Note that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA bit should be set as the final

step of the FLLn enable sequence.

The FLL_SYNC_ENA bit should not be changed if FLLn_ENA = 1; the FLLn_ENA bit should be cleared before changing

FLLn_SYNC_ENA.

The FLL supports configurable free-running operation, using the FLLn_FREERUN register bits described in the next section.

Note that, once the FLL output has been established, the FLL will always free-run when the input reference clock is stopped,

regardless of the FLLn_FREERUN bits.

To disable the FLL while the input reference clock has stopped, the respective FLLn

_FREERUN bit must be set to ‘1’, before

setting the FLLn

_ENA bit to ‘0’.

When changing any of the FLL configuration fields, it is recommended that the digital circuit be disabled via FLLn_ENA and

then re-enabled after the other register settings have been updated. If the FLL configuration is changed while the FLL is

enabled, the respective FLLn_FREERUN bit should be set before updating any other FLL fields. A minimum delay of 32µs

should be allowed between setting FLLn_FREERUN and writing to the required FLL register fields. The FLLn_FREERUN

bit should remain set until after the FLL has been reconfigured.

Note that, if the FLLn_N or FLLn_THETA fields are changed while the FLL is enabled, the FLLn_CTRL_UPD bit must also

be written, as described below. As a general rule, however, it is recommended to configure the FLL (and FLL Synchroniser,

if applicable), before setting the corresponding _ENA register bit(s).

The FLL configuration requirements are illustrated in Figure 76.

CS47L85 Datasheet(PDF) 301 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 301 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL