CS47L85 datasheet(298/370 Pages) CIRRUS

298 / 370 page

CS47L85

298

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ync_clock

7:3

OPCLK_ASYNC_

DIV [4:0]

00h

OPCLK_ASYNC Divider

02h = Divide by 2

04h = Divide by 4

06h = Divide by 6

… (even numbers only)

1Eh = Divide by 30

Note that only even numbered divisions

(2, 4, 6, etc.) are valid selections.

All other codes are Reserved when the

OPCLK_ASYNC signal is enabled.

2:0

OPCLK_ASYNC_

SEL [2:0]

000

OPCLK_ASYNC Source Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related ASYNCCLK rates only

(i.e., ASYNC_SAMPLE_RATE_n =

01XXX).

The OPCLK_ASYNC Source Frequency

must be less than or equal to the

ASYNCCLK frequency.

R334

(014Eh)

Clock_Ge

n_Pad_Ctr

MCLK2_PD

MCLK2 Pull-Down Control

0 = Disabled

1 = Enabled

MCLK1_PD

MCLK1 Pull-Down Control

0 = Disabled

1 = Enabled

R338

(0152h)

Rate_Esti

mator_1

TRIG_ON_STAR

TUP

Automatic Sample Rate Detection Start-

Up select

0 = Do not trigger Write Sequence on

initial detection

1 = Always trigger the Write Sequencer on

sample rate detection

3:1

LRCLK_SRC

[2:0]

000

Automatic Sample Rate Detection source

000 = AIF1LRCLK

001 = Reserved

010 = AIF2LRCLK

011 = Reserved

100 = AIF3LRCLK

101 = Reserved

110 = AIF4LRCLK

111 = Reserved

RATE_EST_ENA

Automatic Sample Rate Detection control

0 = Disabled

1 = Enabled

R339

(0153h)

Rate_Esti

mator_2

4:0

SAMPLE_RATE_

DETECT_A [4:0]

00h

Automatic Detection Sample Rate A

(Up to four different sample rates can be

configured for automatic detection.)

SAMPLE_RATE_n.

R340

(0154h)

Rate_Esti

mator_3

4:0

SAMPLE_RATE_

DETECT_B [4:0]

00h

Automatic Detection Sample Rate B

(Up to four different sample rates can be

configured for automatic detection.)

SAMPLE_RATE_n.

CS47L85 Datasheet(PDF) 298 Page - Cirrus Logic

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