CS47L85 datasheet(294/370 Pages) CIRRUS

294 / 370 page

CS47L85

294

Rev 4.3

The CS47L85 clocking control registers are described in Table 105.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R256

(0100h)

Clock_32k

CLK_32K_ENA

32kHz Clock Enable

0 = Disabled

1 = Enabled

1:0

CLK_32K_SRC

[1:0]

32kHz Clock Source

00 = MCLK1 (direct)

01 = MCLK2 (direct)

10 = SYSCLK (automatically divided)

11 = Reserved

R257

(0101h)

System_Cl

ock_1

SYSCLK_FRAC

SYSCLK Frequency

0 = SYSCLK is a multiple of 6.144MHz

1 = SYSCLK is a multiple of 5.6448MHz

10:8

SYSCLK_FREQ

[2:0]

101

SYSCLK Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 98.304MHz (90.3168MHz)

All other codes are Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only (i.e.,

SAMPLE_RATE_n = 01XXX).

SYSCLK_ENA

SYSCLK Control

0 = Disabled

1 = Enabled

SYSCLK should only be enabled after the

applicable clock source has been

configured and enabled.

Set this bit to 0 when reconfiguring the

clock sources.

All SYSCLK-dependent functions should

be disabled before clearing

SYSCLK_ENA=0. Specific control

sequences must be followed if

reconfiguring SYSCLK while dependent

functions are enabled.

3:0

SYSCLK_SRC

[3:0]

0100

SYSCLK Source

0000 = MCLK1

0001 = MCLK2

0100 = FLL1

0101 = FLL2

0110 = FLL3

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1011 = AIF4BCLK

All other codes are Reserved

CS47L85 Datasheet(PDF) 294 Page - Cirrus Logic

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