CS47L85 datasheet(290/370 Pages) CIRRUS

290 / 370 page

CS47L85

290

Rev 4.3

all DSP functions are configured automatically, with values determined from the SYSCLK_FREQ, SAMPLE_RATE_n,

ASYNC_CLK_FREQ and ASYNC_SAMPLE_RATE_n fields.

Note that the digital audio interface (AIF) clocking rates must be configured separately.

The sample rates of each AIF, the input (ADC) paths, output (DAC) paths and DSP functions are selected as described in

the respective sections. Stereo full-duplex sample rate conversion is supported in multiple configurations to allow digital

audio to be routed between interfaces and for asynchronous audio data to be mixed. See “Digital Core” for further details.

The SYSCLK_SRC register is used to select the SYSCLK source, as described in Table 105. The source may be MCLKn,

AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL

must be enabled and configured, as described later.

The SYSCLK_FREQ and SYSCLK_FRAC registers are set according to the frequency of the selected SYSCLK source.

Note that the FLLn oscillator frequency is divided by three, when used as the SYSCLK source, as shown in Figure 74 and

Figure 76. Accordingly, the FLLs can support SYSCLK frequencies in the range 90MHz to 100MHz.

The SYSCLK-referenced circuits within the digital core are clocked at a dynamically-controlled rate, limited by the SYSCLK

frequency itself. For maximum signal mixing and processing capacity, it is recommended that the highest possible SYSCLK

frequency is configured.

The SAMPLE_RATE_n registers are set according to the sample rate(s) that are required by one or more of the CS47L85

audio interfaces. The CS47L85 supports sample rates ranging from 8kHz to 192kHz.

The SYSCLK signal is enabled by the register bit SYSCLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn)

must be enabled before setting SYSCLK_ENA=1. This bit must be cleared to 0 when reconfiguring the SYSCLK source or

frequency. The SYSCLK_ENA bit should also be cleared to 0 before stopping or removing the applicable clock source.

The SYSCLK signal is the reference clock for many different subsystems on the CS47L85. All of the SYSCLK-dependent

subsystems should be disabled if SYSCLK is not enabled. The SYSCLK_ENA bit must be set to 1 before enabling any

SYSCLK-dependent function, and all the dependent functions should be disabled before clearing the SYSCLK_ENA bit to

The SYSCLK-dependent subsystems are referenced below; if one or more of the following conditions is met, then the

SYSCLK signal is required, and should not be interrupted or reconfigured.



Input signal path enabled (INnx_ENA=1)



Output signal path enabled (OUTnx_ENA=1, SPKOUTx_ENA=1, HPnx_ENA=1)



Digital Core Mixer enabled (*_SRCn>00h)



EQ, DRC, or LHPF processor enabled (EQn_ENA=1, DRCnx_ENA=1, LHPFn_ENA=1)



SPDIF output enabled (SPD1_ENA=1)



Tone generator enabled (TONEn_ENA=1)



Noise generator enabled (NOISE_GEN_ENA=1)



Haptic generator enabled (HAP_CTRL>00)



PWM generator enabled (PWMn_ENA=1)



ASRC channel enabled (ASRCn_INmL_ENA=1, ASRCn_INmR_ENA=1)



ISRC channel enabled (ISRCn_INTm_ENA=1, ISRCn_DECm_ENA=1)



Digital audio interface path enabled (AIFnTXm_ENA=1, AIFnRXm_ENA=1)



Digital audio interface clocks enabled (AIFn_BCLK_FRC=1, AIFn_LRCLK_FRC=1)



SLIMbus framer mode enabled (note - only applies if SLIMCLK_SRC=0)



SLIMbus data channel enabled (SLIMTXn_ENA=1, SLIMRXn_ENA=1)



DSP Core firmware requires access to registers below 0x40000



Timer enabled, with SYSCLK as clock source (TIMERn_RUNNING_STS=1 and TIMERn_REFCLK_SRC=8h)



ANC processor enabled (CLK_L_ENA_SET=1, CLK_NG_ENA=1)



OPCLK enabled for GPIO output (OPCLK_ENA=1)

CS47L85 Datasheet(PDF) 290 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 290 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL