CS47L85 datasheet(289/370 Pages) CIRRUS

289 / 370 page

CS47L85

Rev 4.3

289

SYSCLK AND ASYNCCLK CONTROL

The SYSCLK and ASYNCCLK clocks may be provided directly from external inputs (MCLK, or slave mode BCLK inputs).

Alternatively, the SYSCLK and ASYNCCLK clocks can be derived using the integrated FLL(s), with MCLK, BCLK, LRCLK

or SLIMCLK as a reference.

The required SYSCLK frequency is dependent on the SAMPLE_RATE_n registers. Table 103 illustrates the valid SYSCLK

frequencies for every supported sample rate.

The SYSCLK_FREQ and SYSCLK_FRAC registers are used to identify the applicable SYSCLK frequency. It is

recommended that the highest possible SYSCLK frequency is selected.

The chosen SYSCLK frequency must be valid for all of the SAMPLE_RATE_n registers. It follows that all of the

SAMPLE_RATE_n registers must select numerically-related values, i.e., all from the same cell as represented in Table 103.

Sample Rate

SAMPLE_RATE_

SYSCLK

Frequency

SYSCLK_FREQ

SYSCLK_FRAC

12kHz

24kHz

48kHz

96kHz

192kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz,

98.304MHz

000,

001,

010,

011,

100

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz,

45.1584MHz,

90.3168MHz

000,

001,

010,

011,

100

Note that each of the SAMPLE_RATE_n registers must select a sample rate value from the same

group in the two lists above.

Table 103 SYSCLK Frequency Selection

The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n registers. Table 104 illustrates the

valid ASYNCCLK frequencies for every supported sample rate.

The ASYNC_CLK_FREQ register is used to identify the applicable ASYNCCLK frequency. It is recommended that the

highest possible ASYNCCLK frequency is selected.

Note that, if all the sample rates in the system are synchronised to SYSCLK, then the ASYNCCLK may not be required at

all. In this case, the ASYNCCLK should be disabled (see Table 105), and the associated register values are not important.

Sample Rate

ASYNC_SAMPLE_RATE_n

ASYNCCLK

Frequency

ASYNC_CLK_FREQ

12kHz

24kHz

48kHz

96kHz

192kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz

98.304MHz

000,

001,

010,

011

100

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz,

45.1584MHz

90.3168MHz

000,

001,

010,

011

100

Note that each of the ASYNC_SAMPLE_RATE_n registers must select a sample rate value from

the same group in the two lists above.

Table 104 ASYNCCLK Frequency Selection

The CS47L85 supports automatic clocking configuration. The programmable dividers associated with the ADCs, DACs and

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