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CS47L85 Datasheet(PDF) 293 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 293 Page - Cirrus Logic |
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293 / 370 page  CS47L85 Rev 4.3 293 MCLK2 MCLK1 SYSCLK SYSCLK_ENA AIF1BCLK AIF2BCLK AIF3BCLK CLK_32K_SRC 32k Clock Divider (Auto) Divider OPCLK OPCLK_SEL OPCLK_DIV CLK_32K_ENA OPCLK_ENA Automatic Clocking Control FLLn, AIFnLRCLK, and SLIMCLK can also be selected as FLLn input reference. SYSCLK_SRC SYSCLK_FREQ [2:0] SYSCLK_FRAC SAMPLE_RATE_1 [4:0] SAMPLE_RATE_2 [4:0] SAMPLE_RATE_3 [4:0] ASYNC_CLK_FREQ [2:0] ASYNC_SAMPLE_RATE_1 [4:0] ASYNC_SAMPLE_RATE_2 [4:0] DSP_CLK_FREQ_RANGE [2:0] AIF4BCLK FLL1_REFCLK_SRC FLL2_REFCLK_SRC Divider FLL1_GPCLK_DIV GPIO FLL1_GPCLK_ENA Divider GPIO FLL2_GPCLK_DIV FLL2_GPCLK_ENA DSPCLK FLL3_REFCLK_SRC Divider GPIO FLL3_GPCLK_DIV FLL3_GPCLK_ENA FLL1 FLL2 FLL3 ASYNC_CLK_ENA ASYNCCLK Divider OPCLK_ASYNC OPCLK_ASYNC_SEL OPCLK_ASYNC_DIV OPCLK_ASYNC_ENA ASYNC_CLK_SRC Divide by 3 Divide by 3 Divide by 3 Divide by 2 Divide by 2 Divide by 2 DSP_CLK_ENA DSP_CLK_SRC Divide by 6 Figure 74 System Clocking |
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