CS47L85 datasheet(291/370 Pages) CIRRUS

291 / 370 page

CS47L85

Rev 4.3

291

If reconfiguration of the SYSCLK source or frequency is required, and it is not possible to disable all of the SYSCLK-

dependent subsystems, then the Control Write Sequencer must be used for the reconfiguration of SYSCLK. The control

sequence should apply the following actions:



Clear SYSCLK_ENA to 0



Write updates to SYSCLK_SRC, SYSCLK_FREQ, and SYSCLK_FRAC



Set SYSCLK_ENA to 1

The ASYNC_CLK_SRC register is used to select the ASYNCCLK source, as described in Table 105. The source may be

MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant

FLL must be enabled and configured, as described later.

The ASYNC_CLK_FREQ register is set according to the frequency of the selected ASYNCCLK source. Note that the FLLn

output frequency is divided by three, when used as the ASYNCCLK source. The FLLs can support ASYNCCLK frequencies

in the range 90MHz to 100MHz.

The ASYNCCLK-referenced circuits within the digital core are clocked at a dynamically-controlled rate, limited by the

ASYNCCLK frequency itself. For maximum signal mixing and processing capacity, it is recommended that the highest

possible ASYNCCLK frequency is configured.

The ASYNC_SAMPLE_RATE_n registers are set according to the sample rate(s) of any audio interface that is not

synchronised to the SYSCLK clock domain.

The ASYNCCLK signal is enabled by the register bit ASYNC_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK

or FLLn) must be enabled before setting ASYNC_CLK_ENA=1. This bit must be cleared to 0 when reconfiguring the

ASYNCCLK source or frequency. The ASYNC_CLK_ENA bit should also be cleared to 0 before stopping or removing the

applicable clock source.

The SYSCLK (and ASYNCCLK, when applicable) clocks must be configured and enabled before any audio path is enabled.

The CS47L85 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies are high enough to

support the commanded signal paths and processing functions. If an attempt is made to enable a signal path or processing

function, and there are insufficient SYSCLK or ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note

that any signal paths that are already active will not be affected under these circumstances.)

DSPCLK CONTROL

The DSPCLK clock may be provided directly from external inputs (MCLK, or slave mode BCLK inputs). Alternatively,

DSPCLK can be derived using the integrated FLL(s), with MCLK, BCLK, LRCLK or SLIMCLK as a reference.

Note that a configurable clock divider is provided for each DSP Core, allowing the DSP clocking (and power consumption)

to be optimised according to the applicable processing requirements of each DSP Core. See “DSP Firmware Control” for

further details.

The DSP Cores are clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK

configuration must ensure that sufficient clock cycles are available for the processing requirements of each DSP Core. The

requirements will vary, according to the particular software that is in use.

The DSP_CLK_SRC register is used to select the DSPCLK source, as described in Table 105. The source may be MCLKn,

AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is selected as the source, then the relevant FLL

must be enabled and configured, as described later.

In most cases, the FLL output frequency is divided by two, when used as the DSPCLK source; this enables DSPCLK

frequencies in the range 135MHz to 150MHz. For FLL1 only, a ‘divide by 6’ option is also available, supporting low power

DSP operation with DSPCLK frequencies in the range 45MHz to 50MHz.

The DSPCLK signal is enabled by the register bit DSP_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK or FLLn)

must be enabled before setting DSP_CLK_ENA=1. This bit must be cleared to 0 when reconfiguring the clock sources.

The DSP_CLK_FREQ_RANGE register must be configured for the applicable DSPCLK frequency. Note that, if the DSPCLK

frequency is equal to one of the threshold frequencies quoted, then the higher range setting should be selected. For example,

if the DSPCLK frequency is 37.5MHz, then DSP_CLK_FREQ_RANGE should be set to 011.

In a typical application, DSPCLK and SYSCLK are derived from a single FLL source. In this case, one of the nominal

DSPCLK frequencies is likely to be applicable (see Table 105).

Note that there is no requirement for DSPCLK to be synchronised to SYSCLK or ASYNCCLK. The DSPCLK controls the

software execution in the DSP Cores; audio outputs from the DSP Cores may be synchronised either to SYSCLK or

ASYNCCLK, regardless of the applicable DSPCLK rate.

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