CS47L85 datasheet(287/370 Pages) CIRRUS

287 / 370 page

CS47L85

Rev 4.3

287

CLOCKING AND SAMPLE RATES

The CS47L85 requires a clock reference for its internal functions and also for the input (ADC) paths, output (DAC) paths

and digital audio interfaces. Under typical clocking configurations, all commonly-used audio sample rates can be derived

directly from the external reference; for additional flexibility, the CS47L85 incorporates three Frequency Locked Loop (FLL)

circuits to perform frequency conversion and filtering.

External clock signals may be connected via MCLK1 and MCLK2. (These inputs are referenced to the DBVDD1 and

DBVDD2 power domains respectively.) In AIF Slave modes, the BCLK signals may be used as a reference for the system

clocks. The SLIMbus interface can provide the clock reference, when used as the input to one of the FLLs. To avoid audible

glitches, all clock configurations must be set up before enabling playback.

SYSTEM CLOCKING

The CS47L85 supports three primary clock domains - SYSCLK, ASYNCLK, and DSPCLK.

The SYSCLK and ASYNCCLK clock domains are the reference clocks for all the audio signal paths on the CS47L85. Up to

five different sample rates may be independently selected for specific audio interfaces and other input/output signal paths;

each selected sample rate must be synchronised either to SYSCLK or to ASYNCCLK, as described later.

The SYSCLK and ASYNCCLK clock domains are independent (i.e., not synchronised). Stereo full-duplex sample rate

conversion is supported, allowing asynchronous audio data to be mixed and to be routed between independent interfaces.

See “Digital Core” for further details.

The DSPCLK clock domain is the reference clock for the programmable DSP Cores on the CS47L85. A wide range of

DSPCLK frequencies can be supported, and a programmable clock divider is provided for each DSP Core, allowing the DSP

clocking (and power consumption) to be optimised according to the applicable processing requirements of each DSP Core.

See “DSP Firmware Control” for further details.

Note that there is no requirement for DSPCLK to be synchronised to SYSCLK or ASYNCCLK. The DSPCLK controls the

software execution in the DSP Cores; audio outputs from the DSP Cores may be synchronised either to SYSCLK or

ASYNCCLK, regardless of the applicable DSPCLK rate.

Excluding the DSP Cores, each subsystem within the CS47L85 digital core is clocked at a dynamically-controlled rate,

limited by the SYSCLK (or ASYNCCLK) frequency, as applicable. For maximum signal mixing and processing capacity, it is

recommended that the highest possible SYSCLK and ASYNCCLK frequencies are configured.

The DSP Cores are clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK

configuration must ensure that sufficient clock cycles are available for the processing requirements of each DSP Core. The

requirements will vary, according to the particular software that is in use.

SAMPLE RATE CONTROL

The CS47L85 supports two independent clock domains for the audio signal paths, referenced to SYSCLK and ASYNCCLK

respectively.

Different sample rates may be selected for each of the audio interfaces (AIF1, AIF2, AIF3, AIF4, SLIMbus), and for the input

(ADC) and output (DAC) paths. Each of these must be referenced either to SYSCLK or to ASYNCCLK. (Note that the

SLIMbus interface supports multiple sample rates, selected independently for each input or output channel.)

The CS47L85 can support a maximum of five different sample rates at any time. The supported sample rates range from

8kHz to 192kHz.

Up to three different sample rates can be selected using the SAMPLE_RATE_1, SAMPLE_RATE_2 and SAMPLE_RATE_3

registers. These must each be numerically related to each other and to the SYSCLK frequency (further details of these

requirements are provided in Table 103 and the accompanying text).

The remaining two sample rates can be selected using the ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2

registers. These sample rates must be numerically related to each other and to the ASYNCCLK frequency (further details

of these requirements are provided in Table 104 and the accompanying text),

Each of the audio interfaces, input paths and output paths is associated with one of the sample rates selected by the

SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers.

Note that if any two interfaces are operating at the same sample rate, but are not synchronised, then one of these must be

referenced to the ASYNCCLK domain, and the other to the SYSCLK domain.

Note that, when any of the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers is written to, the activation of the

new setting is automatically synchronised by the CS47L85 to ensure continuity of all active signal paths. The

SAMPLE_RATE_n_STS and ASYNC_SAMPLE_RATE_n_STS registers provide readback of the sample rate selections

that have been implemented.

CS47L85 Datasheet(PDF) 287 Page - Cirrus Logic

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