CS47L85 datasheet(288/370 Pages) CIRRUS

288 / 370 page

CS47L85

288

Rev 4.3

There are some restrictions to be observed regarding the sample rate control configuration, as noted below:



The input (ADC / Digital Microphone) and output (DAC) signal paths must always be associated with the SYSCLK

clocking domain.



All external clock references (MCLK input or Slave mode AIF input) must be within 1% of the applicable register

setting(s).



The input (ADC / DMIC) sample rate is valid from 8kHz to 192kHz. If 384kHz or 768kHz DMIC clock rate is

selected on any of the input paths, then the supported sample rate is valid only up to 48kHz or 96kHz respectively.



The S/PDIF sample rate is valid from 32kHz to 192kHz.



The Asynchronous Sample Rate Converters (ASRCs) support sample rates 8kHz to 192kHz. For each ASRC, the

ratio of the two sample rates must not exceed 6.



The Isochronous Sample Rate Converters (ISRCs) support sample rates 8kHz to 192kHz. For each ISRC, the

higher sample rate must be an integer multiple of the lower rate.

AUTOMATIC SAMPLE RATE DETECTION

The CS47L85 supports automatic sample rate detection on the digital audio interfaces (AIF1, AIF2, AIF3 and AIF4). Note

that this is only possible when the respective interface is operating in Slave mode (i.e., when LRCLK and BCLK are inputs

to the CS47L85).

Automatic sample rate detection is enabled using the RATE_EST_ENA register bit. The LRCLK input pin selected for sample

rate detection is set using the LRCLK_SRC register.

Up to four audio sample rates can be configured for automatic detection; these sample rates are selected using the

SAMPLE_RATE_DETECT_n registers. Note that the function will only detect sample rates that match one of the

SAMPLE_RATE_DETECT_n registers.

If one of the selected audio sample rates is detected on the selected LRCLK input, then a Control Write Sequence will be

triggered. A unique sequence of actions may be programmed for each of the detected sample rates. Note that the applicable

control sequences must be programmed by the user for each detection outcome. See “Control Write Sequencer” for further

details.

The TRIG_ON_STARTUP register controls whether the sample rate detection circuit responds to the initial detection of the

applicable interface (i.e., when the AIFn interface starts up).

When TRIG_ON_STARTUP=0, then the detection circuit will only respond (i.e., trigger the Control Write Sequencer) to a

change in the detected sample rate -

the initial sample rate detection will be ignored. (Note that the ‘initial sample rate

detection’ is the first detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n registers.)

When TRIG_ON_STARTUP=1, then the detection circuit will trigger the Control Write Sequencer whenever a selected

sample rate is detected, including when the AIF interface starts up, or when the sample rate detection is first enabled.

As described above, setting TRIG_ON_STARTUP=0 is designed to inhibit any response to the initial detection of a sample

rate that matches one of the SAMPLE_RATE_DETECT_n registers. Note that, if the LRCLK_SRC setting is changed, or if

the detection function is disabled and re-enabled, then a subsequent detection of a matching sample rate may trigger the

Control Write Sequencer, regardless of the TRIG_ON_STARTUP setting.

There are some restrictions to be observed regarding the automatic sample rate detection, as noted below:



The same sample rate must not be selected on more than one of the SAMPLE_RATE_DETECT_n registers.



Sample rates 192kHz and 176.4kHz must not be selected concurrently.



Sample rates 96kHz and 88.2kHz must not be selected concurrently.

The control registers associated with the automatic sample rate detection function are described in Table 105.

CS47L85 Datasheet(PDF) 288 Page - Cirrus Logic

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