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CS47L85 Datasheet(PDF) 295 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 295 Page - Cirrus Logic

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CS47L85
Rev 4.3
295
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R258
(0102h)
Sample_ra
te_1
4:0
SAMPLE_RATE_
1 [4:0]
10001
Sample Rate 1 Select
00h = None
01h = 12kHz
02h = 24kHz
03h = 48kHz
04h = 96kHz
05h = 192kHz
09h = 11.025kHz
0Ah = 22.05kHz
0Bh = 44.1kHz
0Ch = 88.2kHz
0Dh = 176.4kHz
11h = 8kHz
12h = 16kHz
13h = 32kHz
All other codes are Reserved
R259
(0103h)
Sample_ra
te_2
4:0
SAMPLE_RATE_
2 [4:0]
10001
Sample Rate 2 Select
Register coding is same as
SAMPLE_RATE_1.
R260
(0104h)
Sample_ra
te_3
4:0
SAMPLE_RATE_
3 [4:0]
10001
Sample Rate 3 Select
Register coding is same as
SAMPLE_RATE_1.
R266
(010Ah)
Sample_ra
te_1_statu
s
4:0
SAMPLE_RATE_
1_STS [4:0]
00000
Sample Rate 1 Status
(Read only)
Register coding is same as
SAMPLE_RATE_1.
R267
(010Bh)
Sample_ra
te_2_statu
s
4:0
SAMPLE_RATE_
2_STS [4:0]
00000
Sample Rate 2 Status
(Read only)
Register coding is same as
SAMPLE_RATE_1.
R268
(010Ch)
Sample_ra
te_3_statu
s
4:0
SAMPLE_RATE_
3_STS [4:0]
00000
Sample Rate 3 Status
(Read only)
Register coding is same as
SAMPLE_RATE_1.
R274
(0112h)
Async_clo
ck_1
10:8
ASYNC_CLK_FR
EQ [2:0]
011
ASYNCCLK Frequency
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
100 = 98.304MHz (90.3168MHz)
All other codes are Reserved
The frequencies in brackets apply for
44.1kHz-related sample rates only (i.e.,
ASYNC_SAMPLE_RATE_n = 01XXX).
6
ASYNC_CLK_EN
A
0
ASYNCCLK Control
0 = Disabled
1 = Enabled
ASYNCCLK should only be enabled after
the applicable clock source has been
configured and enabled.
Set this bit to 0 when reconfiguring the
clock sources.



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