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CS47L85 Datasheet(PDF) 299 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 299 Page - Cirrus Logic

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CS47L85
Rev 4.3
299
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R341
(0155h)
Rate_Esti
mator_4
4:0
SAMPLE_RATE_
DETECT_C [4:0]
00h
Automatic Detection Sample Rate C
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
R342
(0156h)
Rate_Esti
mator_5
4:0
SAMPLE_RATE_
DETECT_D [4:0]
00h
Automatic Detection Sample Rate D
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
Table 105 Clocking Control
In AIF Slave modes, it is important to ensure the applicable clock domain (SYSCLK or ASYNCCLK) is synchronised with
the associated external LRCLK. This can be achieved by selecting an MCLK input that is derived from the same reference
as the LRCLK, or can be achieved by selecting the external BCLK or LRCLK signal as a reference input to one of the FLLs,
as a source for SYSCLK or ASYNCCLK.
If the AIF clock domain is not synchronised with the LRCLK, then clicks arising from dropped or repeated audio samples will
occur, due to the inherent tolerances of multiple, asynchronous, system clocks. See “Applications Information” for further
details on valid clocking configurations.



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