CS47L85 datasheet(302/370 Pages) CIRRUS

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CS47L85

302

Rev 4.3

MCLK2

MCLK1

FLLn_REFCLK_SRC

FVCO (270MHz ≤ Fvco ≤ 300MHz)

FOUT (SYSCLK, ASYNCCLK)

Divide by 3

FLLn_ENA (FLL Enable)

FLLn,

AIFnBCLK,

AIFnLRCLK

Divide by 1, 2, 4 or 8

Divide by

FLLn_REFCLK_DIV

FREF < 13.5MHz

FREF

Multiply by

N.K

Multiply by

FLLn_FRATIO

Multiply by

1, 2, 3

… 16

Main FLL path

FLLn_SYNCCLK_SRC

SLIMCLK

SLIMCLK_REF_GEAR

Divide by

FLLn_SYNCCLK_DIV

Divide by 1, 2, 4 or 8

FSYNC < 13.5MHz

FSYNC

Multiply by

N.K (Sync)

Multiply by

FLLn_SYNC_

FRATIO

Multiply by

1, 2, 4, 8 or 16

FLL Synchroniser path

FOUT (GPIO)

Divide by 7, 8 .. 127

Divide by

FLLn_GPCLK_DIV

Divide by 2

FOUT (DSPCLK)

FLLn_SYNC_ENA

(FLL Synchroniser Enable)

Automatic

Divider

N.K = FLLn_N +

FLLn_THETA

FLLn_LAMBDA

N.K (Sync) = FLLn_SYNC_N +

FLLn_SYNC_THETA

FLLn_SYNC_LAMBDA

Synchroniser disabled:

N.K = FLLn_N +

FLLn_THETA

65536

Synchroniser enabled:

Figure 76 FLL Configuration

The procedure for configuring the FLL is described below. Note that the configuration of the main FLL path and the FLL

Synchroniser path are very similar. One or both paths must be configured, depending on the application requirements:



If a single clock input reference is used, then only the main FLL path should be used.



If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, then only the main FLL

path should be used.



If two clock input references are used, then the constant or low-noise clock is configured on the main FLL path,

and the high-accuracy clock is configured on the FLL synchroniser path. Note that the synchroniser input must be

synchronous with the audio data.

The following description is applicable to FLL1, FLL2 and FLL3. The associated register control fields are described in Table

109, Table 110 and Table 111 respectively.

The main input reference is selected using FLLn_REFCLK_SRC. The synchroniser input reference is selected using

FLLn_SYNCCLK_SRC. The available options in each case comprise MCLK1, MCLK2, SLIMCLK, AIFnBCLK, AIFnLRCLK,

or the output from another FLL.

The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The divider automatically adapts

to the

SLIMbus Clock Gear, to provide a constant reference frequency for the FLL. See “SLIMbus Interface Control” for

details.

The FLL input reference can be generated directly from the output of another FLL. Note that the reference frequency is

equal to FVCO / 3 in this case, with respect to the selected FLL source.

The FLLn_REFCLK_DIV field controls a programmable divider on the main input reference. The FLLn_SYNCCLK_DIV field

controls a programmable divider on the synchroniser input reference. Each input can be divided by 1, 2, 4 or 8. These

registers should be set to bring each reference down to 13.5MHz or below. For best performance, it is recommended that

the highest possible frequency - within the 13.5MHz limit - should be selected. (Note that additional guidelines also apply,

as described below.)

The FLL output frequency, relative to the main input reference FREF, is a function of:



The FLL oscillator frequency, FVCO



The frequency ratio set by FLLn_FRATIO



The real number represented by N.K. (N=integer; K=fractional portion)

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