CS47L85 datasheet(304/370 Pages) CIRRUS

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CS47L85

304

Rev 4.3

FLLn_FRATIO

REFERENCE FREQUENCY

FREF - MAXIMUM VALUE

0h (divide by 1)

13.5 MHz

1h (divide by 2)

6.144 MHz

2h (divide by 3)

3h (divide by 4)

3.072 MHz

4h (divide by 5)

5h (divide by 6)

2.8224 MHz

6h (divide by 7)

7h (divide by 8)

1.536 MHz

8h (divide by 9)

9h (divide by 10)

Ah (divide by 11)

Bh (divide by 12)

Ch (divide by 13)

Dh (divide by 14)

Eh (divide by 15)

Fh (divide by 16)

768 kHz

Table 107 Maximum FLL input frequency (function of FLLn_FRATIO)

The value of N is held in the FLLn_N register field.

The value of K is determined by the FLLn_THETA and FLLn_LAMBDA fields, as described later.

The FLLn_N, FLLn_THETA and FLLn_LAMBDA fields are all coded as integers (LSB = 1).

If the FLLn_N or FLLn_THETA registers are updated while the FLL is enabled (FLLn_ENA=1), then the new values will only

be effective when a ‘1’ is written to the FLLn_CTRL_UPD bit. This makes it possible to update the two registers

simultaneously, without disabling the FLL.

Note that, when the FLL is disabled (FLLn_ENA=0), then the FLLn_N and FLLn_THETA registers can be updated without

writing to the FLLn_CTRL_UPD bit.

The values of FLLn_THETA and FLLn_LAMBDA can be calculated as described later.

A similar procedure applies for the derivation of the FLL Synchroniser parameters - assuming that this function is used.

The FLLn_SYNC_FRATIO field selects the frequency division ratio of the FLL synchroniser input. The FLLn_GAIN and

FLLn_SYNC_DFSAT fields are used to optimise the FLL, according to the input frequency. These fields should be set as

described in Table 108.

Note that the FLLn_SYNC_FRATIO register coding is not the same as the FLLn_FRATIO register.

SYNCHRONISER

FREQUENCY FSYNC

FLLn_SYNC_FRATIO

FLLn_SYNC_GAIN

FLLn_SYNC_DFSAT

1MHz - 13.5MHz

0h (divide by 1)

4h (16x gain)

0 (wide bandwidth)

256kHz - 1MHz

1h (divide by 2)

2h (4x gain)

0 (wide bandwidth)

128kHz - 256kHz

2h (divide by 4)

0h (1x gain)

0 (wide bandwidth)

64kHz - 128kHz

3h (divide by 8)

0h (1x gain)

1 (narrow bandwidth)

Less than 64kHz

4h (divide by 16)

0h (1x gain)

1 (narrow bandwidth)

Table 108 Selection of FLLn_SYNC_FRATIO, FLLn_SYNC_GAIN, FLLn_SYNC_DFSAT

The FLL oscillator frequency, FVCO, is the same frequency calculated as described above.

The value of N.K (Sync) can then be determined as follows:

N.K (Sync) = FVCO / (FLLn_SYNC_FRATIO x 3 x FSYNC)

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