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CS47L85 Datasheet(PDF) 300 Page - Cirrus Logic |
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CS47L85 Datasheet(HTML) 300 Page - Cirrus Logic |
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300 / 370 page  CS47L85 300 Rev 4.3 BCLK AND LRCLK CONTROL The digital audio interfaces (AIF1, AIF2, AIF3 and AIF4) use BCLK and LRCLK signals for synchronisation. In master mode, these are output signals, generated by the CS47L85. In slave mode, these are input signals to the CS47L85. It is also possible to support mixed master/slave operation. The BCLK and LRCLK signals are controlled as illustrated in Figure 75 . See the “Digital Audio Interface Control” section for further details of the relevant control registers. Note that the BCLK and LRCLK signals are synchronised to SYSCLK or ASYNCLK, depending upon the applicable clocking domain for the respective interface. See “Digital Core” for further details. AIF1_BCLK_FREQ [4:0] f/N AIF1BCLK AIF1LRCLK AIF1_BCPF [12:0] SYSCLK MASTER MODE CLOCK OUTPUTS f/N AIF1_BCLK_MSTR AIF1_LRCLK_MSTR AIF2_BCLK_FREQ [4:0] f/N AIF2BCLK AIF2LRCLK AIF2_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF2_BCLK_MSTR AIF2_LRCLK_MSTR AIF3_BCLK_FREQ [4:0] f/N AIF3BCLK AIF3LRCLK AIF3_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF3_BCLK_MSTR AIF3_LRCLK_MSTR ASYNCCLK The clock reference for each AIF is SYSCLK or ASYNCCLK AIFn is clocked from SYSCLK if AIFn_RATE < 1000 AIFn is clocked from ASYNCCLK if AIFn_RATE >= 1000 (see note below) (see note below) (see note below) AIF4_BCLK_FREQ [4:0] f/N AIF4BCLK AIF4LRCLK AIF4_BCPF [12:0] MASTER MODE CLOCK OUTPUTS f/N AIF4_BCLK_MSTR AIF4_LRCLK_MSTR (see note below) Figure 75 BCLK and LRCLK Control CONTROL INTERFACE CLOCKING Register map access is possible with or without a system clock - there is no requirement for SYSCLK, or any other system clock, to be enabled when accessing the register map. See “Control Interface” for further details of control register access. |
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