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CS47L85 Datasheet(PDF) 296 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 296 Page - Cirrus Logic

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CS47L85
296
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
3:0
ASYNC_CLK_SR
C [3:0]
0101
ASYNCCLK Source
0000 = MCLK1
0001 = MCLK2
0010 = Reserved
0011 = Reserved
0100 = FLL1
0101 = FLL2
0110 = FLL3
0111 = Reserved
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1011 = AIF4BCLK
All other codes are Reserved
R275
(0113h)
Async_sa
mple_rate
_1
4:0
ASYNC_SAMPL
E_RATE_1 [4:0]
10001
ASYNC Sample Rate 1 Select
00h = None
01h = 12kHz
02h = 24kHz
03h = 48kHz
04h = 96kHz
05h = 192kHz
09h = 11.025kHz
0Ah = 22.05kHz
0Bh = 44.1kHz
0Ch = 88.2kHz
0Dh = 176.4kHz
11h = 8kHz
12h = 16kHz
13h = 32kHz
All other codes are Reserved
R276
(0114h)
Async_sa
mple_rate
_2
4:0
ASYNC_SAMPL
E_RATE_2 [4:0]
10001
ASYNC Sample Rate 2 Select
Register coding is same as
ASYNC_SAMPLE_RATE_1.
R283
(011Bh)
Async_sa
mple_rate
_1_status
4:0
ASYNC_SAMPL
E_RATE_1_STS
[4:0]
00000
ASYNC Sample Rate 1 Status
(Read only)
Register coding is same as
ASYNC_SAMPLE_RATE_1.
R284
(011Ch)
Async_sa
mple_rate
_2_status
4:0
ASYNC_SAMPL
E_RATE_2_STS
[4:0]
00000
ASYNC Sample Rate 2 Status
(Read only)
Register coding is same as
ASYNC_SAMPLE_RATE_1.
R288
(0120h)
DSP_Cloc
k_1
10:8
DSP_CLK_FREQ
_RANGE [2:0]
000
DSPCLK Frequency
000=5.5MHz to 9.375MHz (9.216MHz)
001=9.375MHz to 18.75MHz (18.432MHz)
010=18.75MHz to 37.5MHz (36.864MHz)
011=37.5MHz to 75MHz (73.728MHz)
100=75MHz to 150MHz (147.456MHz)
All other codes are Reserved
The frequencies in brackets are the
nominal (or typical) frequencies for each
setting.
If the DSPCLK frequency is equal to one
of the threshold frequencies quoted (e.g.,
37.5MHz), then the higher range setting
(e.g., 011) should be selected.



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