CS47L85 datasheet(303/370 Pages) CIRRUS

303 / 370 page

CS47L85

Rev 4.3

303

The FVCO frequency must be in the range 270MHz to 300MHz.

When the FLL is selected as SYSCLK or ASYNCCLK source, a fixed divider sets the output frequency equal to FVCO / 3.

Therefore, FVCO must be exactly 294.912MHz (for 48kHz-related sample rates) or 270.9504MHz (for 44.1kHz-related sample

rates).

When the FLL is selected as DSPCLK source, a fixed divider sets the output frequency equal to FVCO / 2. This enables

DSPCLK frequencies in the range 135MHz to 150MHz. For FLL1 only, a ‘divide by 6’ option is also available, supporting

low power DSP operation with DSPCLK frequencies in the range 45MHz to 50MHz. Note that the DSPCLK can be further

divided for each DSP.

When the FLL is selected as a GPIO output, a programmable divider supports division ratios in the range 7 through to 127,

enabling a wide range of GPIO clock output frequencies.

Note that the chosen FVCO frequency can be used to support multiple outputs simultaneously (e.g., SYSCLK and DSPCLK);

each of the FLL clock output paths is controlled by a separate divider function, as illustrated in Figure 76.

The FLLn_FRATIO field selects the frequency division ratio of the FLL input. The FLLn_GAIN field is used to optimise the

FLL, according to the input frequency. As a general guide, these fields should be selected as described in Table 106. (Note

that additional guidelines also apply, as described below.)

REFERENCE

FREQUENCY FREF

FLLn_FRATIO

FLLn_GAIN

1MHz - 13.5MHz

0h (divide by 1)

4h (16x gain)

256kHz - 1MHz

1h (divide by 2)

2h (4x gain)

128kHz - 256kHz

3h (divide by 4)

0h (1x gain)

64kHz - 128kHz

7h (divide by 8)

0h (1x gain)

Less than 64kHz

Fh (divide by 16)

0h (1x gain)

Table 106 Selection of FLLn_FRATIO and FLLn_GAIN

The FLL oscillator frequency, FVCO is set according to the following equation:

FVCO = (FREF x 3 x N.K x FLLn_FRATIO)

The value of N.K can thus be determined as follows:

N.K = FVCO / (FLLn_FRATIO x 3 x FREF)

Note that, in the above equations:

FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable

FLLn_FRATIO is the FVCO clock ratio (1, 2, 3 … 16)

If the above equations produce an integer value for N.K, then the value of FLLn_FRATIO should be adjusted to a different,

odd-number division (e.g., divide by 3), and the value of N.K re-calculated. A non-integer value of N.K is recommended for

best performance of the FLL. (If possible, the FLLn_FRATIO value should be decreased to the nearest alternative odd-

number division. If a suitable lower value does not exist, FLLn_FRATIO should be increased to the nearest odd-number

division instead.)

After the value of FLLn_FRATIO has been determined, the input frequency, FREF, must be compared with the maximum

frequency limit noted in Table 107. If the input frequency (after division by FLLn_REFCLK_DIV) is higher than the applicable

limit, then the FLLn_REFCLK_DIV division ratio should be increased, and the value of N.K re-calculated. (Note that the

same value of FLLn_FRATIO as already calculated should be used, when deriving the new value of N.K.)

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