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AD7380 Datasheet(PDF) 6 Page - Analog Devices |
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AD7380 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 33 page ![]() Data Sheet AD7383-4/AD7384-4 SPECIFICATIONS analog.com Rev. 0 | 6 of 33 Table 4. All Devices (Continued) Parameter Test Conditions/Comments Min Typ Max Unit Normal Mode (Static) 155 400 nA Normal Mode (Operational) 7.6 8.9 mA Shutdown Mode 155 400 nA Power Dissipation PVCC Normal Mode (Static) 9.3 11.5 mW Shutdown Mode 375 720 µW VLOGIC Power (PVLOGIC) Analog inputs at positive full scale Normal Mode (Static) 0.55 1.4 µW Normal Mode (Operational) 27.3 31.8 mW Shutdown Mode 0.55 1.4 µW TIMING SPECIFICATIONS VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V, and TA = −40°C to +125°C, unless otherwise noted. When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed, such as ALERT. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Table 5. Timing Specifications Parameter Min Typ Max Unit Description tCYC 250 ns Time between conversions tSCLKED 5 ns CS falling edge to first SCLK falling edge tSCLK 12.5 ns SCLK period tSCLKH 5.5 ns SCLK high time tSCLKL 5.5 ns SCLK low time tCSH 20 ns CS pulse width tQUIET 20 ns Interface quiet time prior to conversion tSDOEN 5.5 ns CS low to SDOA and SDOB enabled tSDOH 3 ns SCLK rising edge to SDOA and SDOB hold time tSDOS 5 ns SCLK rising edge to SDOA and SDOB setup time tSDOT 8 ns CS rising edge to SDOA and SDOB high impedance tSDIS 4 ns SDI setup time prior to SCLK falling edge tSDIH 4 ns SDI hold time after SCLK falling edge tSCLKCS 0 ns SCLK rising edge to CS rising edge tCONVERT 190 ns Conversion time tACQUIRE 110 ns Acquire time tRESET 250 ns Valid time to start conversion after soft reset 800 ns Valid time to start conversion after hard reset tPOWERUP Supply active to conversion 5 ms First conversion allowed 11 ms Settled to within 1% with internal reference 5 Settled to within 1% with external reference tREGWRITE 5 ms Supply active to register read write access allowed tSTARTUP Exiting shutdown mode to conversion 10 µs Settled to within 1% with external reference tCONVERT0 6 8 10 ns Conversion time for first sample in OS normal mode tCONVERTx Conversion time for xth sample in OS normal mode, 4 MSPS, 16-bit devices tCONVERT0 + (320 × (x – 1)) ns For AD7383-4 tCONVERT0 + (250 × (x – 1)) ns For AD7384-4 |
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