AD7380 datasheet(23/33 Pages) AD

23 / 33 page

Data Sheet

AD7383-4/AD7384-4

INTERFACE

analog.com

Rev. 0 | 23 of 33

The interface to the AD7383-4/AD7384-4 is via a SPI. The interface

consists of the CS, SCLK, SDOA, SDOB, SDOC, SDOD, and SDI

pins. When referencing a single function of a multifunction pin, only

the portion of the pin name that is relevant to the specification is

listed, such as SDOD. For full pin names of multifunction pins, refer

to the Pin Configuration and Function Descriptions section.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-hold

into hold mode, at which point the analog input is sampled, and the

bus is taken out of three-state. The ADC conversion operation is

driven internally by an on-board oscillator and is independent of the

SCLK signal.

The SCLK signal synchronizes data in and out of the device via

the SDOA, SDOB, SDOC, SDOD, and SDI signals. A minimum of

16 SCLK cycles are required for a write to or read from a register.

The minimum number of SCLKs for a conversion read is dependent

on the resolution of the device and the configuration settings (see

Table 14).

The AD7383-4/AD7384-4 have four serial output signals, SDOA,

SDOB, SDOC, and SDOD. Programming the SDO bit in the CON-

FIGURATION2 register configures 4-wire, 2-wire, or 1‑wire mode.

To achieve the highest throughput of the devices, use either the

2-wire or 4-wire mode to read the conversion results. If a reduced

throughput is required or oversampling is used, it is possible to use

1-wire mode, SDOA signal only, for reading conversion results.

Configuring a cyclic redundancy check (CRC) operation for SPI

reads, SPI writes, and oversampling mode with resolution boost

mode enabled alters the operation of the interface. Refer to the

CRC section to ensure correct operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low

transition on the CS signal initiates a simultaneous conversion

of the four ADCs, ADC A, ADC B, ADC C, and ADC D. The

AD7383-4/AD7384-4 have a one cycle readback latency. Therefore,

the conversion results are available on the next SPI access. Take

the CS signal low, and the conversion result clocks out on the serial

data output pins. The next conversion is also initiated at this point.

The conversion result is shifted out of the device as a 16-bit result

for the AD7383-4 and 14-bit result for the AD7384-4. The MSB of

the conversion result is shifted out on the CS falling edge. The

remaining data is shifted out of the device under the control of the

SCLK input. The data is shifted out on the rising edge of the SCLK,

and the data bits are valid on both the falling edge and the rising

edge. After the final SCLK falling edge, take CS high again to return

the SDOx to a high impedance state.

The number of SCLK cycles to propagate the conversion SDOx

pins is dependent on the serial mode of operation configured and

if resolution boost mode is enabled (see Figure 34 and Table 14

for details). If CRC reading is enabled, additional SCLK pulses are

required to propagate the CRC information (see the CRC section

for more details).

Because the CS signal initiates a conversion as well as framing the

data, any data access must be completed within a single frame.

Table 14. Number of SCLK Cycles (n) Required for Reading Conversion Results

Interface Configuration

Resolution Boost Mode

CRC Read

No. of SCLK Cycles

4-Wire

Disabled

Enabled

Disabled

Enabled

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

Figure 34. Reading Conversion Results

AD7380 Datasheet(PDF) 23 Page - Analog Devices

AD7380 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL